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CHAPTER 3 CPU AND CONTROL UNITS
■ Internal Architecture
The FR CPU uses the Harvard architecture, in which the instruction bus and data buses are
independent of each other.
A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface
between the CPU and peripheral resources. A Harvard ↔ Princeton bus converter is connected
to the I-bus and D-bus to provide an interface between the CPU and the bus controller.
Figure 3.2-1 shows connections in the internal architecture.
Data
RAM
32 bits
16 bits
Bus converter
16
R-bus
Peripheral resources
32
Figure 3.2-1 Internal Architecture
D-bus
I address
D address
D data
Address
Data
Internal I/O
FRex CPU
I-bus
32
32
I data
32
32
32
32
F-bus
External address
Harvard
24
External data
16
Princeton
bus
converter
Bus controllers
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