Time-Base Timer Control Register - Fujitsu MB90390 Series Hardware Manual

11.2

Time-base Timer Control Register

The time-base timer control register controls interrupts of the time-base timer and can
clear the time-base counter.
■ Time-base Timer Control Register (TBTC)
Figure 11.2-1 Configuration of the Time-base Timer Control Register (TBTC)
Address:
0000A9
H
R/W
R/W : Readable and writable
W : Write only (read always returns "0")
X : Undefined value
- : Undefined
: Initial value
15 14 13 12 11 10
- -
- - R/W R/W W
Initial value
9 8
1 X X 0 0 1 0 0
R/W R/W
bit9 bit8
TBC1 TBC0
0 0
0 1
1 0
1 1
bit10
TBR
0
1
bit11
TBOF
0 no interrupt
1 interrupt request
bit12
TBIE
0 disable Interrupt
1 enable Interrupt
bit13
-
-
bit14
-
-
bit15
Reserved
0
1 always write "1" to this bit
CHAPTER 11 TIME-BASE TIMER
B
Time-base Timer Interval Control
1.024 ms (at 4 MHz)
4.096 ms (at 4 MHz)
16.384 ms (at 4 MHz)
131.072 ms (at 4 MHz)
Time-base Timer Reset
Read Write
clear all bits to "0"
always "1"
no effect
Time-base Timer Interrupt Request Flag
Read Write
clear this bit
no effect
Time-base Timer Interrupt Enable
Undefined
-
Undefined
-
Reser ved
-
179