Clock Control Register (Iccr) - Fujitsu MB91319 Series Hardware Manual

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CHAPTER 15 I C INTERFACE
15.2.3

Clock Control Register (ICCR)

This section describes the configuration and functions of the clock control register
(ICCR).
■ Clock Control Register (ICCR)
Figure 15.2-7 shows the bit configuration of the clock control register (ICCR).
Figure 15.2-7 Bit Configuration of the Clock Control Register (ICCR)
Address:
ch0 0000BE
ch1 0000CE
ch2 0000DE
ch3 0000EE
[bit15] Test bit
This bit is used for testing.
Be sure to write 0 to it.
[bit14] NSF (NoiSe Filter enable)
Input noise filter enable bit.
0
1
Set to "1" when used at speed of 100Kbps or more.
[bit13] EN (ENable)
This bit is the enable bit for the I
0
1
If this bit is set to 0, all bits of the IBSR and IBCR registers (except the BER and BEIE bits) are
cleared. This bit is cleared when a bus error occurs (IBCR BER = 1).
Note:
If this bit is set to 0 (disabled), the I
298
15
H
TEST
H
W
H
Initial value
H 0
Noise filter disabled
Noise filter enabled
2
C interface.
Disabled
Enabled
2
C interface immediately stops sending and receiving.
14 13 12 11
NSF EN CS4 CS3
R R/W R/W R/W
0 0 1 1
10 9 8
CS2 CS1 CS0
R/W R/W R/W
1 1 1