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2
CHAPTER 15 I
C INTERFACE
15.2.9
Clock Disable Register (IDBL)
This section describes the configuration and functions of the clock disable register
(IDBL).
■ IDBL (Clock Disable Register)
Address:
ch0 0000BF
ch1 0000CF
ch2 0000DF
ch3 0000EF
[bit0] IDBL (Clock Disable Bit)
This bit set enable disable of the operation clock supply for I
at the low-power consumption mode.
0: Supply the I
1: Stop the I
This bit is initialized to "0" by reset.
When the bit is set to "1", the read values are undefined without the register, and write is
invalid without the bit (the register).
Note:
If the bit is set to "1", I
■ IFN (FIFO Data Count Register)
Address:
ch0 0000B0
ch1 0000C0
ch2 0000D0
ch3 0000E0
[bit12 to 8] FN4 to FN0 (FIFO data count)
The number of data stored in FIFO is shown.
If this register is 00
full.
When under-run of over-run is occurred, 11
306
Figure 15.2-13 IDBL (Clock Disable Register)
7
H
-
H
H
R
H
Initial value
-
2
C clock
2
2
C clock. I
C line is opened.
2
C operation is stop.
Figure 15.2-14 IFN (FIFO Data Count Register)
15
H
H
R
H
0
H
Initial value
, it indicates the data is empty in FIFO and if it is 10
H
6
5
4
3
-
-
-
-
R
R
R
R
-
-
-
-
2
14
13
12
11
FN4
FN3
R
R
R
R
0
0
0
0
to 1F
is shown.
H
H
2
1
0
-
-
DBL
R
R
R/W
-
-
0
C interface. This bit can be used
10
9
8
FN2
FN1
FN0
R
R
R
0
0
0
, it indicates the FIFO
H
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