Fujitsu MB91319 Series Hardware Manual page 306

Fr60 32-bit microcontroller
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2
CHAPTER 15 I
C INTERFACE
❍ Reception of 7-bit address master
During slave address transmission, FIFO is not used. Write the slave address into IDAR and set
MSS=1.
INT is set to 1 (INT=1) after transmitting the slave address. While INT=1, set receiving data
amount into FIFO register (IFRN), and then set INT=0. FIFO captures the amount of data as set
in the IFRN register. For each byte received, FRN of the IFRN register is decremented, and
when IFRN.FRN value becomes 0 (IFRN.FRN=0), INT is set to 1(INT=1, IFCR.FRED=1). Read
out all data in the FIFO from the IFDR while INT=1.
To receive data continuously, set the IFRN register with the FIFO empty, and then set INT=0. To
stop the transfer, set MSS=0 (INT is set to 0 (INT=0) automatically).
If FACK=0 is set in the IFRN register, an acknowledge is not generated for the last receiving data
(when IFRN.FRN=1).
❍ Reception of 10-bit address master
During slave address transmission, FIFO is not used. Write the primary slave address into IDAR
and set MSS=1. INT is set to 1 (INT=1) after transmitting the primary slave address. Then, write
the secondary slave address into the IDAR and set INT=0.
transmitting the secondary slave address. After that, read 8th bit of the primary slave address
and write it into the IDAR, and set SSC=1.
INT is set to 1 (INT=1) after transmitting the slave address. While INT=1, set receiving data
amount into FIFO register (IFRN), and then set INT=0. FIFO captures the amount of data as set
in the IFRN register. For each byte received, FRN of the IFRN register is decremented, and
when IFRN.FRN value becomes 0 (IFRN.FRN=0), INT is set to 1(INT=1, IFCR.FRED=1). Read
out all data in the FIFO from the IFDR while INT=1.
To receive data continuously, set the IFRN register with the FIFO empty, and then set INT=0. To
stop the transfer, set MSS=0 (INT is set to 0 (INT=0) automatically).
If FACK=0 is set in the IFRN register, an acknowledge is not generated for the last receiving data
(when IFRN.FRN=1).
❍ Transmission of 7-bit address slave
INT is set to 1 (INT=1) after receiving slave address (slave address is not captured into FIFO). If
data of arbitrary byte length is written into IFDR while INT=1, the data is stored in the FIFO.
When INT is set to 0 (INT=0) after writing the data, the amount of data written in the FIFO is
transmitted.
transmission data continuously and set INT=0. These processes will be repeated until the master
outputs a repeat "START" condition or a "STOP" condition.
When either a repeat "START" condition or a "STOP" condition is detected, TED of the IFCR is
set to 1. In this case, SCL is not set to L. Clear the FIFO if there is any remaining data in it.
Write 0 into TED, and end the FIFO.
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When the FIFO is emptied, INT is set to 1(INT=1, IFCR.TFE=1).
INT is set to 1 (INT=1) after
Write the

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