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READING THIS MANUAL
■ Terms Used in This Manual
The following defines principal terms used in this manual.
Term
I-bus
D-bus
F-bus
X-bus
R-bus
E-unit
CLKP
CLKB
CLKT
32-bit bus for internal instructions. In the FR family, which is based on an
internal Harvard architecture, independent buses are used for instructions and
data. A bus converter is connected to the I-bus.
Internal 32-bit data bus. An internal resource is connected to the D-bus.
Princeton bus on which internal instructions and data are multiplexed. The F-bus
is connected via a switch to the I-bus and D-bus. Built-in resources such as
ROM and RAM are connected to the F-bus.
External interface bus. An external interface module is connected to the X-bus.
Data and instructions are multiplexed on the external data bus.
Internal 16-bit data bus. The R-bus is connected to the D-bus via an adapter. I/
O, a clock generator, and an interrupt controller are connected to the R-bus.
Since addresses and data are multiplexed on an R-bus that is only 16 bits wide,
more than one cycle is required for the CPU to access these resources.
Execution unit for operations.
System clock. Clock generated by the clock generator for each of the internal
resources connected to the R-bus. This clock has the same frequency as the
source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,...
or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divide-
by rate specified by the B3 to B0 bits in the clock generator DIV0 register.
System clock. Operating clock for the CPU and each of the other resources
connected to a bus other than the R-bus and X-bus. This clock has the same
frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/
4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as
determined by the divided-by rate specified by the P3 to P0 bits in the clock
generator DIV0 register.
System clock. Operating clock for the external bus interface connected to the X-
bus. This clock has the same frequency as the source oscillation at its
maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/
6, ... or 1/32) frequency clock as determined by the divide-by rate specified by
the T3 to T0 bits in the clock generator DIV1 register.
Meaning
v
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