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[bit25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode
This bit specifies the address processing of the transfer source address of the corresponding
channel for each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer
operation according to the specified transfer source address count width (SASZ). When the
transfer is completed, the next access address is written to the corresponding address register
(DMASA).
As a result, the transfer source address register is not updated until DMA transfer is
completed.
To make the address always the same, specify 0 or 1 for this bit and set the address count
width (SASZ and DASZ) to 0.
Table 16.2-8 shows the specification of the transfer source address count mode.
Table 16.2-8 Specification of the Transfer Source Address Count Mode
SADM
0
Increments the transfer source address. (initial value)
1
Decrements the transfer source address.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[bit24] DADM (Destination-ADdr. Count-Mode select)*:Transfer destination address count
This bit specifies the address processing for the transfer destination address of the
corresponding channel in each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer
operation according to the specified transfer destination address count width (DASZ). When
the transfer is completed, the next access address is written to the corresponding address
register (DMADA).
As a result, the transfer destination address register is not updated until the DMA transfer is
completed.
To make the address always the same, specify 0 or 1 for this bit and set the address count
width (SASZ and DASZ) to 0.
Table 16.2-9 shows the specification of the transfer destination address count mode.
Table 16.2-9 Specification of the Transfer Destination Address Count Mode
DADM
0
Increments the transfer destination address. (initial value)
1
Decrements the transfer destination address.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
CHAPTER 16 DMA CONTROLLER (DMAC)
specification
Function
mode specification
Function
331
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