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CHAPTER 3 CPU AND CONTROL UNITS
❍ ILM
The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM
is used as a level mask.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level
indicated in this ILM.
The highest level is 0 (00000
The program setting range is limited.
•
When the original value is between 16 and 31:
A new value between 16 and 31 can be set. If an instruction that sets a value between 0 and
15 is executed, the specified value plus 16 is transferred.
•
When the original value is between 0 and 15:
Any value between 0 and 31 can be set.
Reset initializes this bit to 15 (01111
❍ Program counter (PC)
PC
[bit31 to bit0]
These are the bits of the program counter that indicates the address of the instruction being
executed.
Bit0 is set to 0 when the PC is updated after an instruction is executed. Bit0 can become 1
only if the branch address is an odd number address.
However, even if the branch address is an odd number address, bit0 is invalid and therefore
the instruction should be placed at an even number address.
The initial value after reset is undefined.
❍ Table base register (TBR)
The table base register holds the first address of the vector table to be used during EIT
processing.
The initial value after reset is 000FFC00
40
20
19
ILM4 ILM3
ILM2
), and the lowest level is 31 (11111
B
31
31
TBR
18
17
16
[Initial value]
ILM1
ILM0
).
B
.
H
01111
B
).
B
0 [Initial value]
XXXXXXXX
H
0 [Initial value]
000FFC00
H
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