A/Dc Control Register (Adcth, Adctl) - Fujitsu MB91319 Series Hardware Manual

CHAPTER 12 10-BIT A/D CONVERTER
12.2.1

A/DC Control Register (ADCTH, ADCTL)

This section explains the configuration and functions of the A/DC control register
(ADCTH, ADCTL).
■ A/DC Control Register (ADCTH, ADCTL)
Figure 12.2-2 shows the bit configuration of the A/DC control register (ADCTH, ADCTL).
Figure 12.2-2 Bit Configuration of the A/DC Control Register (ADCTH, ADCTL)
15
ADCTH
"0"
(R)
7
ASS3
ADCTL
(R)
[bit15 to bit10] Don't Care
The read value of these bits is always 0.
[bit9] TRG
When this bit is set to 1, A/D conversion is started when a rising edge is detected at external
pin ATGX.
This bit is ignored if an edge is detected during A/D conversion.
0
1
[bit8] STR
This bit is the A/D conversion start bit.
The read value of this bit is always 0.
0
1
[bit7 to bit4] ASS3 to ASS0
These bits enable reading of the selected analog channel.
This bit enables reading of effective data when [bit3] BUSY = 1.
0 to 7
242
14 13 12
"0" "0" "0"
(R) (R) (R)
6 5 4
ASS2 ASS1 ASS0
(R) (R) (R)
Start by external pin trigger is prohibited.
Start by external pin trigger
No effect
Software start/stop (write during conversion)
Selected channel
11 10 9
"0" "0" TRG
(R) (R) (R/W)
3 2 1
BUSY "0" INT
(R) (R) (R/W)
Initial value
8
STR 0000 0000
B
(R/W)
Initial value
0
INTE
0000 0000
B
(R/W)