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[Example]
LDI:32
JMP:D
LDI:8
...
RP referenced by the RET:D instruction is not affected even though RP is updated by the
instruction in the delay slot.
[Example]
RET:D
MOV
...
The flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delay slot.
[Example]
ADD
BC:D
ANDCCR
...
If RP is referenced by an instruction in the delay slot of the CALL:D instruction, the data that has
been updated by the CALL:D instruction is read.
[Example]
CALL:D
MOV
...
❍ Instructions that can be placed in the delay slot
Only an instruction meeting the following conditions can be executed in the delay slot.
•
One-cycle instruction
•
Instruction other than a branch instruction
•
Instruction whose operation is not affected even though the order is changed
A one-cycle instruction is an instruction denoted in the Number of Cycles column in the list of
instructions as 1, a, b, c, and d.
#Label,
R0
@R0
;
Branch to Label
#0,
R0
;
No effect on the branch destination address
;
Branch to address defined beforehand in RP
R8,
RP
;
No effect on the return operation
#1,
R0
;
Flag change
Overflow
;
Branch to execution result of above instruction
#0
;
This flag update is not referenced by the
above branch instruction.
Label
;
Updating RP and branching
RP,
R0
;
Transferring RP, execution result of above
CALL:D
CHAPTER 3 CPU AND CONTROL UNITS
47
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