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Fujitsu MB86617A Specification Sheet

Ieee1394 serial bus controller for dtv.
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LSI Specification
MB86617A
IEEE1394 Serial Bus Controller
for DTV
MB86617A
LSI Specification
Rev. 1.0
August 16, 2001
i
Rev.1.0
Fujitsu VLSI

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   Summary of Contents for Fujitsu MB86617A

  • Page 1

    LSI Specification MB86617A IEEE1394 Serial Bus Controller for DTV MB86617A LSI Specification Rev. 1.0 August 16, 2001 Rev.1.0 Fujitsu VLSI...

  • Page 2: Table Of Contents

    ...7 NTERFACE <D ...7 RIDGE CHAPTER 4 PIN ASSIGN MENT... 8 ... 9 4.1. P SSIGNMENT 4.2.C MB86617A P ORRESPONDING ABLE OF 4.3. O UTLINE RAWING OF ACKAGE CHAPTER 5 PIN FUNCTION ... 12 ... 13 5.1. IEEE1394 I NTERFACE ...

  • Page 3

    EADER NDICATE EGISTER ... 61 [A] ... 62 TATUS EGISTER [B] ... 65 TATUS EGISTER ... 68 EGISTER ... 69 EGISTER MB86617A ... 32 [A] ... 44 ACKET EADER ETTING EGISTER [B] ... 45 ACKET EADER ETTING EGISTER Fujitsu VLSI...

  • Page 4

    ) ... 90 READ ) ... 91 READ WRITE ) ... 92 READ WRITE )... 93 ) ... 94 READ ) ... 95 READ ) ... 96 READ WRITE )... 97 )... 98 )... 99 )... 100 MB86617A Fujitsu VLSI...

  • Page 5

    ... 103 & EGISTER INTERRUPT MASK ETTING ... 120 ...122 ... 125 ...128 1934 P ) ... 131 FOR ONE PORT ...132 ABLE OWER UPPLY PLL L ...133 UILD ILTER ...134 IRCUIT AT RYSTAL SCILLATOR MB86617A ...107 EGISTER Fujitsu VLSI...

  • Page 6: Chapter 1 Overview

    MB86617A has two exclusive ports (one is the combined use for receiving a message of interface for DV) for MPEG2 and DSS data transfer, and performs isolating and packeting of Header and Data department with these two ports automatically. This function is suited for maintaining continuum of transfer.

  • Page 7: Chapter 2 Features

    LSI S pecification Chapter 2 Features This chapter explains the features of MB86617A. > Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft > Integrates PHY and LINK layers into single-chip > 1394 port number : 3 ports >...

  • Page 8: Chapter 3 Chip Block

    LSI S pecification Chapte r 3 Chip Block This chapter explains the MB86617A block diagram and the function of each block. 3.1. Block Diagram 3.2. Function of Each Block Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 9: Block Diagram

    LSI S pecification 3.1. Block Diagram MB86617A block diagram is shown below. < Normal Operation Mode < Asynch Transmit Exclusive FIFO (256 byte) Asynch Transmit Packet Process Asynch Transmit Packet Process Asynch Transmit Exclusive FIFO (256 byte) FIFO (2KByte) FIFO...

  • Page 10: Synchronous Ransmit Fifo Extended Ode

    FIFO CP IC (2KByte) Interface Fig.3.1.2 Block Diagram - Asynchronous Transmit FIFO Extended Mode - Rev.1.0 PHY/ LINK Layer FIFO Control (2KByte Circuit FIFO (2KByte) MB86617A TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 TPA2 XTPA2 TPB2 XTPB2...

  • Page 11: Synchronous Eceive Fifo Extended Ode

    FIFO CP IC (2KByte) Interface Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode - Rev.1.0 PHY/ LINK Layer FIFO Control (2KByte Circuit FIFO (2KByte) MB86617A TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 TPA2 XTPA2 TPB2 XTPB2...

  • Page 12: Function Of Each Block

    LSI S pecification 3.2. Function of Each Block This section explains the function of each block for MB86617A. < PHY Layer Control Circuit < This circuit is for the Physical layer of IEEE 1394 with the following functions. > Asynchronous transfer is supported under cable environment.

  • Page 13: Chapter 4 Pin Assignment

    LSI S pecification Chapter 4 Pin Assignment This chapter explains the pin assignment and table of pin function of MB86617A. 4.1. Pin Assignment 4.2. Corresponding Table of MB86617A Pin 4.3. Outline Drawing of Package Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 14: Pin Assignment

    LSI S pecification 4.1. Pin Assignment The following diagram shows the MB86617A pin assignment. XRESET MODE1 MODE0 XWR(XDS) XRD(R/XW) XINT DREQ XDACK TEST1 TEST2 AVSS AVDD AVSS AVDD Rev.1.0 M B 8 6 6 1 7 F P T - 1 7 6 P - M 0 3...

  • Page 15: Corresponding Table Of Mb86617a Pin

    LSI S pecification 4.2. Corresponding Table of MB86617A Pin The following table shows the corresponding items of MB86617A pin. Pin Name XRESET MODE1 MODE0 XWR(XDS) XRD(R/XW) XINT DREQ XDACK TEST1 TEST2 AVSS AVDD AVSS AVDD Rev.1.0 Pin Name AVSS AVDD...

  • Page 16: Outline Drawing Of Package

    LSI S pecification MB86617A 4.3. Outline Drawing of Package This section shows the outline drawing of MB86617A package (LQFP -176). Rev.1.0 Fujitsu VLSI...

  • Page 17: Chapter 5 Pin Function

    LSI S pecification Chapter 5 Pin Function This chapter explains the MB86617A pin function. 5.1. IEEE1394 Interface 5.2. Isochronous (TSP-IC,DV -IC) Interface 5.4. MPU Interface 5.5. Other Pins 5.6. Power/GND Pin Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 18: Ieee1394 Interface

    I/O pin of TPB - (minus) signal on cable port 2 Output pin of reference voltage for common voltage on cable port 0 Output pin of reference voltage for common voltage on cable port 1 Output pin of reference voltage for common voltage on cable port 2 MB86617A Fujitsu VLSI...

  • Page 19: Isochronous Interface

    Input signal for enable signal of Isochronous data Output Isochronous- FIFO data to data output pin while this signal in active. Switch data synchronizing with rise edge of ICLK Output pin of time stamp trigger signal ‘L’ active signal MB86617A Fujitsu VLSI...

  • Page 20

    Output pin for noticing error of receive data (on port A) ‘H’ active signal Output pin for noticing error of receive data (on port B) ‘H’ active signal Clock input pin for DSS data (27MHz) Clock input pin for DSS data (27MHz) MB86617A Fujitsu VLSI...

  • Page 21: Mpu Interface

    Input pin of ALE signal to be output with its address in available when selecting multiplex mode When selecting non-multiplex mode, set this signal in fixed ‘L’ Output pin of DMA transfer requiring signal for DMAC Input pin of DMA allowance signal from DMAC Output pin for interruption request MB86617A Fujitsu VLSI...

  • Page 22: Other Pins

    IEEE1394 cable. When PMODE becomes ‘H’, ‘L’ is output. With the PMODE in ‘H’, the output of this pin is not changed. If not using this pin, set this pin as open one. This pin is for test. Use this pin as open one. MB86617A Fujitsu VLSI...

  • Page 23: Power/gnd Pin

    LSI S pecification 5.6. Power/GND Pin This section explains the power/GND pin. Signal Name AVDD AVSS Rev.1.0 Function 3.3V digital power pin Digital ground pin 3.3V analog power pin Analog ground pin MB86617A Fujitsu VLSI...

  • Page 24: Chapter 6 Internal Register

    LSI S pecification Chapter 6 Internal Register This chapter explains the MB86617A internal register. Note that the access of internal register is applied only 16 bits access. WRITE Address (HEX) Register Name mode-control (reserved) Instruction-fetch Interrupt-mask setting [A] Interrupt-mask setting [B]...

  • Page 25

    Late packet criterion range setting [B] receive Isochronous packet header indicate 1 [A] receive Isochronous packet header indicate 2 [A] receive Isochronous packet header indicate 3 [B] receive Isochronous packet header indicate 4 [B] FIFO reset data bridge transmit/receive status [A] MB86617A Fujitsu VLSI...

  • Page 26

    Isochronous channel monitor 4 cycle-time-monitor (upper) cycle-time-monitor (lower) Ping time monitor PHY/LINK register address setting PHY/LINK register access port Revision indicate register (upper) Revision indicate register (lower) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) MB86617A Fujitsu VLSI...

  • Page 27

    Register Name transmit CGMS/TSCH indicate [A] transmit CGMS/TSCH indicate [B] transmit CGMS/TSCH indicate status transmit EMI/OE setting (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) MB86617A Fujitsu VLSI...

  • Page 28

    (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) Rev.1.0 READ Register Name (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) MB86617A Fujitsu VLSI...

  • Page 29

    Register Name (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) Rev.1.0 READ Register Name (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) MB86617A Fujitsu VLSI...

  • Page 30: Chapter 7 Internal Register Function Description

    LSI S pecification Chapter 7 Internal Register Function Description This chapter explains the details of the internal register of MB86617A. 7.1. mode-control Register 7.2. flag & status Register 7.3. instruction fetch Register 7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register 7.5. Receive Acknowledge Indicate Register 7.6.

  • Page 31

    7.33. PHY/LINK Register/Address Setting Register 7.34. PHY/LINK Register/Access Port 7.35. Revision Indicate Register 7.36. Transmit CGMS/TSCH Indicate Register [A] 7.37. Transmit CGMS/TS CH Indicate Register [B] 7.38. Transmit CGMS/TSCH Indicate Status Register 7.39. Transmit EMI/OE Setting Register Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 32: M Ode-control Register

    TSSYNCA and TSSYNCB signals are asserted when the data is outputted from TSP interface. Always indicate ‘0’. Always write in ‘0’. Clears receive Isochronous-FIFO when bus reset occurred. Does not clear Isochronous-FIFO when bus reset occurred. MB86617A Iso-FI Asyn- send/re FO no FIFOs stand- ‘0’...

  • Page 33

    Uses 2K byte FIFO for Asynchronous receive with Asyn-FIFO sel (bit3) ‘1’. Activates TSP -IC I/F terminal output. Disables TSP-IC I/F terminal output, and brings it in high impedance status. Activates CP I/F terminal output. Disables CP I/F terminal output, and brings it in high impedance status. MB86617A Function Fujitsu VLSI...

  • Page 34: Flag & Status Register

    Indicates that Asynchronous transmit specific buffer is not empty. Indicates that Asynchronous transmit specific buffer is empty. Indicates that Asynchronous receive specific buffer is not empty. Indicates that Asynchronous receive specific buffer is empty. Always indicate ‘0’. MB86617A data recv sleep cmstr busy ‘0’...

  • Page 35

    Indicates that packet receive is in busy mode due to receipt of Asynchronous packet and self-ID packet. Indicates that node is not the cycle master now. Node is the cycle master now. Interrupt indicate register does not have interrupt. Interrupt indicate register has interrupt. MB86617A Function Fujitsu VLSI...

  • Page 36: I Nstruction Fetch R Egister

    Note) Before writing in instruction for this register, read out IPC busy Bit (bit15) of “7.2. flag & status Register”, and confirm that the IPC busy value is ‘0’. Rev.1.0 “00 h” Value Specify each instruction code. Specify required operand for each instruction code. Write ‘0’ into all bits for instructions without operand. MB86617A operand “00 h” Function Fujitsu VLSI...

  • Page 37: R Egister

    After reading out this register, clear to ‘0’ automatically. Do not mask interrupt factors. Mask interrupt factors. Interrupt factors masked by setting of this register are neither stored in interrupt indicate register nor assert INT signal. MB86617A ‘0’ ‘0’ ‘0’ ‘0’...

  • Page 38: Receive Acknowledge Indicate Register

    Value Always indicate ‘0’. Indicate code of received Acknowledge packet addressed to it. (MSB: bit7, LSB: bit5) Indicate parity of received Acknowledge packet addressed to it. (MSB: bit3, LSB: bit0) MB86617A Receive ack-code Receive ack-parity “0 h” “0 h” Function...

  • Page 39: A-buffer Data Port Receive/transmit

    ASYNC Receive Specific Buffer Data ASYNC Transmit Specific Buffer Data Undefined Action Value Read out port of Asynchronous receive specific buffer. Read (MSB: bit15, LSB: bit0) Write in port of Asynchronous transmit specific buffer. Write (MSB: bit15, LSB: bit0) MB86617A Function Fujitsu VLSI...

  • Page 40: Tsp Transmit Information Setting Register [a

    Set TSCH classification ID to be stored at FIFO of bridge-Ach. (MSB: bit12, LSB: bit7) Processes transmit data as MPEG2-TS. Processes transmit data as DSS packet. Processes transmit DSS packet as 140 byte. Processes transmit DSS packet as 130 byte. MB86617A input set EMI-A form D S S select...

  • Page 41

    Does not mask port A input of TSP-IC interface. Read in input data from port A at transmit. Masks port A input of TSP -IC interface. Does not read in input data from port A at transmit. MB86617A Function Fujitsu VLSI...

  • Page 42: Tsp Transmit Information Setting Register [b

    (MSB: bit12, LSB: bit7) Processes transmit data as MPEG2 -TS packet. Processes transmit data as DSS packet. Processes transmit DSS packet as 140 byte. Processes transmit DSS packet as 130 byte. MB86617A input set EMI-B form D S S select...

  • Page 43

    Does not mask port B input of TSP-IC interface. Reads in input data from port A at transmit. Masks port B input of TSP-IC interface. Does not read in input data from port A at transmit. MB86617A Function Fujitsu VLSI...

  • Page 44: Transmit Offset Setting Register [a

    Set value to be added to cycle-count range of cycle-time-monitor. Setting range is 0h to FFh. (unit=125 S). Set value to be added to cycle-offset range of cycle-time-monitor. Setting range is 0h to C00h. (unit=1/24.576 MHz). MB86617A transmit-offset-A (high) Function Fujitsu VLSI...

  • Page 45: Transmit Offset Setting Register [b

    Set value to be added to cycle-count range of cycle-time-monitor. Setting range is 0h to FFh. (unit=125 S). Set value to be added to cycle-offset range of cycle-time-monitor. Setting range is 0h to C00h. (unit=1/24.576MHz). MB86617A transmit-offset-B (high) Function Fujitsu VLSI...

  • Page 46: Tsp Receive Information Setting Register

    ISO packet header and CIP header are indicated in register. Allows receiving DV data. Deletes received data and reports FMT error when DSS data is received. ISO packet header and CIP header are indicated in register. Allows receiving DSS data. MB86617A output D S S K S L size-A ‘0’...

  • Page 47

    Outputs to port A when TSCMP (bit0) is ‘1’. Outputs to port B when TSCMP (bit0) is ‘1’. Does not merge packet received by Ach and Bch. Outputs to one TSP-IC after merging packets received by Ach and Bch. MB86617A Function Fujitsu VLSI...

  • Page 48

    TSP -IC I/F Port A TV1A Processing-Ach Receive data Processing-Bch Receive data Processing-Ach Receive data Processing-Bch Receive data Processing-Ach+Bc Receive data MB86617A TSP -IC I/F Port B Processing-Ach Receive data Processing-Bch Receive data Processing-Bch Receive data Processing-Ach Receive data Processing-Ach+Bc Receive data...

  • Page 49: R Egister [a]

    Indicates EF range of received DSS packet header. Write in EF range of transmits DSS packet header. Indicates reserved range of received DSS packet header. Write in reserved range of transmit DSS packet header. MB86617A Reserved reserved Function Fujitsu VLSI...

  • Page 50: R Egister [b]

    Indicates EF range of received DSS packet header. Write in EF range of transmit DSS packet header. Indicates reserved range of receive DSS packet header. Write in reserved range of transmit DSS packet header. MB86617A reserved reserved Function Fujitsu VLSI...

  • Page 51: Tsp Status Register

    Indicates that transmit data length input from TSP IC I/F is not consistent with specified format data length. Deletes transmit data without writing into FIFO. Clears to ‘0’ by lead of this register. MB86617A Tx-len FIFO F I F O...

  • Page 52

    Indicates transmit data length input from TSP IC I/F is normal. Indicates transmit data length input from TSP IC I/F is not consistent with specified format data length. Deletes transmit data without writing into FIFO. Clears to ‘0’ by lead of this register. Always indicate ‘0’. MB86617A Function Fujitsu VLSI...

  • Page 53: Data Bridge Transmit Information Setting Register 1 [a

    MPEG2-TS at transmit: “00000110” b DSS at transmit: “00001001” b Write in FN range of transmit CIP header. (MSB: bit1, LSB: bit0) MPEG2-TS at transmit: “11” b DSS at transmit: “10” b MB86617A Tx DBS-A Tx FN-A “00 h” “00 b” Function...

  • Page 54: Data Bridge Transmit Information Setting Register 2 [a

    Write in transmit packet speed. (MSB: bit2, LSB: bit1) s100 at transmit: “00” b s200 at transmit: “01” b s400 at transmit: “10” b Always indicates ‘0’. Always writes in ‘0’. MB86617A Tx channel-A Tx speed-A “00” h “00” b Function Fujitsu VLSI...

  • Page 55: Data Bridge Transmit Information Setting Register 3 [b

    MPEG2-TS at transmit: “00000110” b DSS at transmit: “00001001” b Write in FN range of transmit CIP header. (MSB: bit1, LSB: bit0) MPEG2-TS at transmit: “11” b DSS at transmit: “10” b MB86617A Tx DBS-B Tx FN-B “00 h” “00 b” Function...

  • Page 56: Data Bridge Transmit Information Setting Register 4 [b

    Write in transmit packet speed. (MSB: bit2, LSB: bit1) s100 at transmit: “00” b s200 at transmit: “01” b s400 at transmit: “10” b Always indicates ‘0’. Always writes in ‘0’. MB86617A Tx channel-B Tx speed-B “00” h “00” b Function Fujitsu VLSI...

  • Page 57: Data Bridge Receive Information Setting Register

    Automatically clears when receive process is stopped by bridge -Ach after setting at ‘1’. Stops receive process by bridge -Ach. Write in Isochronous packet channel to be received by bridge-Ach (MSB: bit5, LSB: bit0) MB86617A Rx channel-A ‘0’ “00 h” Function...

  • Page 58: Transmit Packet Link/split Setting Register

    Selects Tx o/e-B b (bit6) setting value as odd/even range of Isochronous packet header to be transmitted by bridge-Bch Write in odd/even range of transmit Isochronous packet header. Valid with o/e select-B (bit7) setting value ‘1’, and reads in this setting value to transmit Isochronous packet header. MB86617A SPQA o/e-A ‘0’ ‘0’...

  • Page 59

    With more than 3 SP, executes according to setting. Executes 5 SP combined transmission at FIFO FULL. Write in number of links for source packet processed by bridge-Ach. Write in number of links for source packet processed by bridge-Ach. MB86617A Function Fujitsu VLSI...

  • Page 60: Late Packet Decision Range Setting Register [a

    Rev.1.0 late range-A “0000 h ” Value Write in Late packet decision range. Setting range is 0h to FFh (unit: 125 S). Write in Late packet decision range. Setting range is 0h to C0h (unit: 16/24.576MHz). MB86617A Function Fujitsu VLSI...

  • Page 61: Late Packet Decision Range Setting Register [b

    Rev.1.0 late range-B “0000 h ” Value Write in Late packet decision range. Setting range is 0h to FFh (unit: 125 S). Write in Late packet decision range. Setting range is 0h to C0h (unit: 16/24.576MHz). MB86617A Function Fujitsu VLSI...

  • Page 62: R Eceive I Sochronous P Acket H Eader I Ndicate R Egister 1 [a]

    Indicate EMI range of receive Isochronous packet header. (MSB: bit8, LSB: bit7) Indicates odd/even range of receive Isochronous packet header. Indicate SI range of CIP header of receive Isochronous packet. (MSB: bit8, LSB: bit3) MB86617A Rx SID-A o/e-A ‘0’ “00 h”...

  • Page 63: R Eceive I Soc Hronous P Acket H Eader I Ndicate R Egister 2 [a]

    Indicates 50/60 range of receive Isochronous packet CIP header when receiving Indicates TSF range of receive Isochronous packet CIP header when receiving MPEG2-TS or DSS. Indicate STYPE range of CIP header of receive Isochronous packet. (MSB: bit4, LSB: bit0) MB86617A Rx STYPE-A 56-A ‘0’ “00 h”...

  • Page 64: R Eceive I Sochronous P Acket H Eader I Ndicate R Egister 3 [b]

    Indicate EMI range of receive Isochronous packet header. (MSB: bit8, LSB: bit7) Indicates odd/even range of receive Isochronous packet header. Indicate SI range of CIP header of receive Isochronous packet. (MSB: bit5, LSB: bit0) MB86617A Rx SID-B o/e-B ‘0’ “00 h”...

  • Page 65: R Eceive I Sochronous P Acket H Eader I Ndicate R Egister 4 [b]

    Indicates 50/60 range of receive Isochronous packet CIP header when receiving Indicates TSF range of receive Isochronous packet CIP header when receiving MPEG2-TS or DSS. Indicate STYPE range of CIP header of receive Isochronous packet. (MSB: bit4, LSB: bit0) MB86617A Rx STYPE-B 56-B ‘0’ “00 h”...

  • Page 66: Fifo Reset Setting Register

    Releases FIFO reset on TSP -IC I/F side of bridge-Ach. Resets FIFO on TSP-IC I/F of bridge-Ach. Releases FIFO reset on LINK-I/F side of bridge-Ach. Resets FIFO on LINK I/F side of bridge-Ach. Always indicate ‘0’. Always write in ‘0’. MB86617A reset reset FIFO- FIFO- ‘0’...

  • Page 67: Data Bridge Transmit/receive Status Register [a

    Indicates that odd/even information of received Isochronous packet header is not changed. Indicates that odd/even information of received Isochronous packet header has changed from just former odd/even information of packet received by Isochronous-cycle. Clears to ‘0’ by lead of this register. MB86617A Rx 56 FIFO stype FIFO err-A...

  • Page 68

    Indicates that DBC range of CIP header of received Isochronous packet is normal. Indicates that DBC range of CIP header of received Isochronous packet received is not consecutive. Clears to ‘0’ by lead of this register. MB86617A Function Delete packet, and not Fujitsu VLSI...

  • Page 69

    Indicates that FMT range of CIP header of received Isochronous packet is other than the value allowed to be received at DV-EN, DSS-EN or TS- EN (1Ch – bit10 to 8) (DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’). Clears to ‘0’ by reading of this register. MB86617A Function Fujitsu VLSI...

  • Page 70: Data Bridge Transmit/receive Status Register [b

    Indicat es that odd/even information of receive Isochronous packet header is not changed. Indicates that odd/even information of receive Isochronous packet header has changed from just former odd/even information of packet received by Isochronous-cycle. Clears to ‘0’ by lead of this register. MB86617A Rx 56 FIFO stype FIFO err-B...

  • Page 71

    Indicates that DBC range of CIP header of received Isochronous packet is normal. Indicates that DBC range of CIP header of received Isochronous packet is not consecutive. Clears to ‘0’ by lead of this register. MB86617A Function Delete packet, and not Fujitsu VLSI...

  • Page 72

    Indicates that FMT range of CIP header of received Isochronous packet is other than the value allowed to be received at DV-EN, DSS-EN or TS- EN (1Ch – bit10 to 8) (DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’). Clears to ‘0’ by reading of this register. MB86617A Function Fujitsu VLSI...

  • Page 73: Isochronous Channel Monitor Register

    Indicate that ‘1’ at Bit corresponding to channel number of Isochronous packet flowing through 1394 bus. 52h-bit15 - 0: channel0 - channel15 54h-bit15 - 0: channel16 - channel31 56h-bit15 - 0: channel32 - channel47 58h-bit15 - 0: channel48 - channel63 MB86617A Function Fujitsu VLSI...

  • Page 74: Cycle-timer-monitor Indicate Register

    To read out this register, make sure to read out in the order of 5C h Rev.1.0 cycle-timer-monitor (hi) cycle-timer-monitor (lo) “0000 h” Value Indicate value of built-in cycle-timer register. (MSB: bit15, LSB: bit0) 5A h, two as a set. MB86617A Function Fujitsu VLSI...

  • Page 75: Ping Time Monitor Register

    Ping time 15 - 0 Read monitor Rev.1.0 Ping time monitor “0000 h ” Value Indicate time period from transmitting request packet to receiving response packet to the request. Counts by 20ns unit. (MSB: bit15, LSB: bit0) MB86617A Function Fujitsu VLSI...

  • Page 76: Phy/link Register/address Setting Register

    Read/ 6 - 0 phy/link-addr Write Rev.1.0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Value Always indicate ‘0’. Always write in ‘0’. Set address of PHY/LINK register to be accessed. (MSB: 6, LSB: 0) MB86617A phy/link-addr “00 h” Function Fujitsu VLSI...

  • Page 77: Phy/link R Egister A Ccess P Ort

    Indicates PHY/LINK register contents defined by address set by PHY/LINK register/address setting register. (MSB: 15, LSB: 0) Executes write in the process of register defined by this address set by PHY/LINK register/address setting register. (MSB: 15, LSB: 0) MB86617A Function Fujitsu VLSI...

  • Page 78: Revision Indicate Register

    Revision indicate register is the register that indicates chip revision of this LSI. Initial Value Bit Name Action 15 - 0 Revision code Read Rev.1.0 Revision code (hi) Revision code (lo) Fixed Value Indicate Revision code. (MSB: bit15, LSB: bit0) MB86617A Function Fujitsu VLSI...

  • Page 79: T Ransmit Cgms/tsch I Ndicate R Egister [a]

    Indicates CGMS information for source packet indicated in TSCHA-1 (bit5 to 0). (MSB: bit7, LSB: bit6) Indicates ID of TS type for source packet input first from port A at TSP IC I/F (MSB: bit5, LSB: bit0) MB86617A TSCHA-1 “00 h” Function...

  • Page 80: T Ransmit Cgms/tsch I Ndicate R Egister [b]

    Indicates CGMS information for source packet indicated in TSCHB-1 (bit5 to 0). (MSB: bit7, LSB: bit6) Indicates ID of TS type for source packet input first from port B at TSP IC I/F (MSB: bit5, LSB: bit0) MB86617A TSCHB-1 “00 h” Function...

  • Page 81: Transmit Cgms/tsch Indicate Status Register

    Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is invalid. Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is valid. Clears to ‘0’ by writing “1”. Always indicate ‘0’. Always write in ‘0’. MB86617A act - vld-T HA-2 ‘0’ ‘0’ ‘0’...

  • Page 82

    Clears to ‘0’ by writing “1”. Indicates that the value indicated in CGMSA-1 and TSCHA-1 (80h-bit7 to 0) is invalid. Indicates that the value indicated in CGMSA-1 and TSCHA-1 (80h-bit7 to 0) is valid. Clears to ‘0’ by writing “1”. MB86617A Function Fujitsu VLSI...

  • Page 83: Transmit Emi/oe Setting Register

    Selects the setting value of IPH EMI-A (bit6 to 5) and IPH OE-A (bit 4) as EMI information and Odd/Even value added to IPH of empty packet until valid data is transmitted after starting transmission. MB86617A IPH EMI-A “00 b”...

  • Page 84

    Set Odd/Even value which is set in IPH of empty packet transmitted from bridge-Ach. Valid only when IPH select-A (bit7) is set to ‘1’. EMI information after transmitting valid data depends on the setting of o/e select-A (3Eh-bit8). Always indicate ‘0’. Always write in ‘0’. MB86617A Function Fujitsu VLSI...

  • Page 85: Chapter 8 Phy/ink Register Function Description

    Physical Register#0D, 0E, 0F 8.11. Physical Register#10 8.12. Physical Register#11, 12, 13 8.13. Physical Register#14, 15, 16 8.14. Physical Register#17, 18, 19, 1A, 1B, 1C, 1D, 1E 8.15. Link Register#00 8.16. Link Register#01 8.17. Link Register#02 8.18. Link Register#03 Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 86: Phy/link R Egister T Able

    Physical register #08 (reserved) Physical register #09 (reserved) Physical register #10 (reserved) Physical register #11 (reserved) Physical register #12 (reserved) Physical register #13 (reserved) Physical register #14 (reserved) Physical register #15 (reserved) Physic al register #16 MB86617A Read Fujitsu VLSI...

  • Page 87

    Physical register #17 Physical register #18 Physical register #19 Physical register #1A Physical register #1B Physical register #1C Physical register #1D Physical register #1E Link register #00 Link register #01 Link register #02 Link register #03 Rev.1.0 Write MB86617A Read Fujitsu VLSI...

  • Page 88: P Hysical Register #00 ( Read )

    Effective after completion of bus reset. Indicates that this node is not root. Indicates that this node is root. Indicates that the supplied cable power is below specification. Indicates that the supplied cable power is over specification. MB86617A Physical_ID “00 h” ‘0’ Function Fujitsu VLSI ‘0’...

  • Page 89: P Hysical Register #01 ( Read / Write )

    Does not perform bus reset. Performs bus reset. Automatically clears to “0” at the completion of bus reset. Indicate current gap-count value (MSB: 5 , LSB: 0). Set gap-count value (MSB: 5 , LSB: 0). MB86617A Gap_count ‘0’ “3F h”...

  • Page 90: P Hysical Register #02 ( Read )

    Indicate that this node has the extended PHY register map. (MSB: 7 , LSB: 5) Always indicate fixed value “7 h”. Always indicates ‘0’. Indicate the number of ports held by this node (MSB: 4 , LSB: 0). Always indicate fixed value “3 h”. MB86617A Extended Total_ports “7 h” ‘0’...

  • Page 91: P Hysical Register #03 ( Read )

    Indicate max. transfer speed supporting PHY of this node (MSB: 7 , LSB: 5). Always indicates fixed value “010 b” (= S400). Always indicates ‘0’. Indicate Delay value at the receive signal repeat (MSB: 3 , LSB: 0). Always indicate fixed value “0000 b”. MB86617A Delay ‘1’ ‘0’ ‘0’...

  • Page 92: P Hysical Register #04 ( Read / Write )

    (MSB : 5 , LSB : 3) Always indicates fixed value “000 b”. Always write in ‘0’. Set pwr field (POWER_CLASS) value of Self-ID packet automatically transmitted by this node with the system power ON. MB86617A Jitter Conte Pwr_class nder ‘1’...

  • Page 93: P Hysical Register #05 ( Read / Write )

    Clears the bit value to ‘0’ by writing in ‘1’. Indicates that timeout is not detected by arbitration state machine. Indicates that timeout is det ected by arbitration state machine. Clears the bit value to ‘0’ by writing in ‘1’. MB86617A Time Port_ Enab...

  • Page 94

    Indicates that resume processing was performed when Resume_Int bit is set at ‘1’. Clears the bit value to ‘0’ by writing in ‘1’. Disables arbitration acceleration function. Enables arbitration acceleration function. Disables multi-speed packet concatenation function. Enables multi-speed packet concatenation function. MB86617A Function Fujitsu VLSI...

  • Page 95: P Hysical Register #07, 08, 09 ( Read )

    Indicates that 1394 port n is parent port. Indicates that 1394 port n is children port. Indicates that cable is not connected to 1394 port n. Indicates that cable is connected to 1394 port n. Always indicate ‘0’ MB86617A Child - C o nnec Bstate-0 ted -0...

  • Page 96: P Hysical Register #0a, 0b, 0c ( Read / Write )

    Always write in ‘0’. Indicates that bias voltage is not detected at 1394 port n. Indicates that bias voltage is detected at 1394 port n. Always indicates ‘0’. Enables 1394 port n. Disable 1394 port n. MB86617A Bias-0 Bias-1 Bias-2 ‘0’ ‘0’...

  • Page 97: P Hysical Register #0d, 0e, 0f ( Read / Write )

    Indicates ‘1’ at Port_event bit when Connected, Bias, Disabled, Fault bit changed. Indicates that suspend or resume processing is normal. Indicates that suspend or resume processing occurred error. Clears the bit value to ‘0’ by writing in ‘1’. Always indicates’0’. Always write in ‘0’. MB86617A Int_en Fault-0 able-0 Int_en Fault-1...

  • Page 98: P Hysical Register #10 ( Read )

    7 - 0 Read evel Rev.1.0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Value Always indicate ‘0’. Indicate that this node supports P1394a standard. (MSB: 7 , LSB: 0) Always indicate fixe value “01 h”. MB86617A Compliance_level “01 h” Function Fujitsu VLSI...

  • Page 99: P Hysical Register #11, 12, 13 ( Read )

    ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Value Always indicate ‘0’. Indicate Vendor ID of Fujitsu (MSB: 7, LSB: 0). Always indicate fixed value “00000E h”. MB86617A Vendor_ID-hi “00 h” Vendor_ID-mid “00 h” Vendor_ID-lo “0E h” Function Fujitsu VLSI...

  • Page 100: P Hysical Register #14, 15, 16 ( Read )

    ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Value Always indicate ‘0’. Indicate Product ID of this chip (MSB: 7, LSB: 0). Always indicate fixed value “086617 h”. MB86617A Product_ID-hi “08 h” Product_ID-mid “66 h” Product_ID-lo “17 h” Function Fujitsu VLSI...

  • Page 101: P Hysical Register #17, 18, 19, 1a, 1b, 1c, 1d, 1e ( Read / Write )

    7 - 0 Free_RAM Write Rev.1.0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Value Always indicates’0’. Always write in ‘0’. Range of 8 bit X 8 Free RAM. MB86617A Free_RAM-0 Free_RAM-1 Free_RAM-2 Free_RAM-3 Free_RAM-4 Free_RAM-5 Free_RAM-6 Free_RAM-7 “00 h” Function Fujitsu VLSI...

  • Page 102: L Ink Register #00 ( Read / Write )

    Always write in ‘0’. Does not cycle master. Operates as cycle master if it is root. Sets the value of this bit at ‘1’ by writing in ‘1’. Always indicate ‘0’. Always w rite in ‘0’. MB86617A cycl e master ‘0’ ‘1’ ‘0’...

  • Page 103: L Ink Register #01 ( Read / Write )

    Always write in ‘0’. Does not cycle master. Performs as cycle master if it is root. Sets the value of this bit at ‘0’ by writing in ‘1’. Always indicate ‘0’. Always write in ‘0’. MB86617A cycl e master ‘0’ ‘1’ ‘0’...

  • Page 104: L Ink Register #02 ( Read / Write )

    Code value of Acknowledge packet automatically transmitted when error is detected depends on the kind of error. Always indicates ‘0’. Always write in ‘0’. LINK layer is disabled. LINK layer is enabled. Always indicates ‘0’. Always write in ‘0’. MB86617A Link Enable mode ‘0’ ‘0’ ‘0’ ‘1’...

  • Page 105: L Ink Register #03 ( Read / Write )

    ‘0’ ‘0’ ‘0’ ‘0’’ Value Always indicate ‘0’. Always write in ‘0’. Releases initialize of LINK layer. Initializes LINK layer. Releases reset of LINK layer. Resets LINK layer. MB86617A Link init ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Function Fujitsu VLSI...

  • Page 106: Chapter 9 Instructio N

    LSI S pecification Chapter 9 Instruction This chapter explains the instruction codes and details for respective instructions. 9.1. Instruction Code Table 9.2. Description of Each Instruction Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 107: I Nstruction C Ode T Able

    9.1. Instruction Code Table Instruction name Start sleep Remove sleep Asynchronous receive Remove busy mode Send PHY packet Asynchronous Send Data-FIFO init DMA Transmit (Asynchronous) DMA Transmit (PHY packet) DMA Receive Rev.1.0 code Operand Speed code FIFO select code MB86617A Fujitsu VLSI...

  • Page 108

    When packet transmit operation is completed normally, this instruction report s the interrupt of “Physical packet send” (INT25). Store the transmit data at ASYNC transmit specific buffer beforehand. Logical inverse part is added automatically by this device. Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 109

    Specify transmit Speed code . (MSB: 1, LSB: 0) = S100 = S200 = S400 = (reserved) Meaning Specify buffer to be cleared. (MSB: 7, LSB: 0) “11 h” = ASYNC receive specific buffer “12 h” = ASYNC transmit specific buffer Other than above (reserved) MB86617A Fujitsu VLSI...

  • Page 110

    This instruction reads out the data stored in ASYNC receive specific FIFO using DMA transfer. Issue Asynchronous receive instruction (03h) before issuing this instruction. Assert DREQ signal after issuing this instruction. Negate DREQ signal when ASYNC receive specific FIFO is empty. Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 111

    LSI S pecification Chapter 10 Interrupt This chapter explains the inturrput-factors and method for interrupt-mask. 10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register 10.2. Interrupt 10.3. Description of Interrupt Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 112

    This register masks the interrupt reported by this device. Do not report the interrupt if ‘1’ is set for Bit corresponding to interrupt factor. Rev.1.0 interrupt-mask Interrupt-mask ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ MB86617A ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Fujitsu VLSI ‘0’...

  • Page 113

    Receive EMI or ODD/EVEN changed First packet received Cycle start packet received Cycle start packet send Physical packet send Extended PHY packet received Physical configuration packet received Link-on packet received Self-ID packet received Receive late occurred Instruction abort Transmit late occurred MB86617A Fujitsu VLSI...

  • Page 114

    >The value of DBC range at CIP header is discontinuous. >Header error in CIP header. >The value of FMT range at CIP header is other than that allowed to be received at DV-EN, DSS-EN or TS -EN (1Ch-bit10 to 8) (DV= ‘000000’, MPEG2-TS=‘100000’, DSS=‘100001’). MB86617A Fujitsu VLSI...

  • Page 115

    Not returned Acknowledge packet in correspondance with Asynchronous packet of non-broadcast sent from self-node within specified limit. Completed sending Acknowledge packet. Changede EMI data or ODD/EVEN value of received Isochronous packet. Received the first packet after setting receive ISO channel. MB86617A Fujitsu VLSI...

  • Page 116

    >Issued “ Remove sleep” (02h) instruction in spite of not in sleep condition. >Issued “Instruction suspend”(62h) instruction without instruction to be stopped. >Used undefine operand against issued instruction. >Issued instruction was undefined. etc. Transmit-late was occured. >Delete packet transmitted. MB86617A Fujitsu VLSI...

  • Page 117

    This chapter explains the operation of this device and displays the examples of control flow. 11.1. Initialization 11.2. Self-ID Packet Receiving 11.3. Asynchronous Packet Transmitting 11.4. Asynchronous Packet Receiving 11.5. Isochronous Packet Transmitting 11.6. Isochronous Packet Receiving Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 118

    Inner reset and release reset. Start bus reset process. Report Bus reset detected(INT4) interrupt (assert Complete bus reset process. Report Bus reset complete (INT3) Figure 11.1 Example of flow for Initialization MB86617A System power ON Start internal PLL. Receive BUS_RESET XINT). interrupt (assert XINT).

  • Page 119

    LSI S pecification 11.2. Self-ID Packet Receiving The example of control flow for receiving Self -ID packet is shown below. 11.2.1 Self-ID Packet Receive during Bus Reset Process 11.2.2 Self-ID Packet Receive after Ping Packet Transmitting Rev.1.0 MB86617A Fujitsu VLSI...

  • Page 120

    11.2.1 This section explains the receiving process of Self-ID packet. The MB86617A device is capable of receiving self-ID packets that each mode transmit in the self-identity stage of bus reset process. When ‘1’ is written to the s-ID store bit of mode- control register (refer to 7.1), the self-ID packet in the bus reset process can be received and the data removing the logical inverse section is stored in the Asynchronous receive- FIFO and Asynchronous transmit -FIFO (512 bytes maxixum).

  • Page 121

    Set FIFO according to FIFO mode. Clear Asynchronous receive buffer. (Note 1) recv busy bit=0 Store received Self-ID packet to Asynchronous receive buffer. Bus reset completed. Report Bus reset completed (INT3) (assert XINT) interrupt. recv busy bit=1 MB86617A Fujitsu VLSI...

  • Page 122

    Prepare for reading received data. Read one word of the received data and increment the read pointer of buffer. Receive Remove busy(04h) instruction. recv busy bit=0 Clear the receive Asynchronous buffer and set FIFO according to FIFO mode. (Note 2) MB86617A Fujitsu VLSI...

  • Page 123

    Read Asynchronous transmit buffer. Arbitration procedure Arbitration result Transmit Ping packet. Report Physical packet send interrupt (INT25) (assert XINT). Store received Self-ID packet in Asynchronous receive buffer. recv busy=1 Report Self-ID packet received interrupt(INT29) (assert XINT) (XINT MB86617A Lost Fujitsu VLSI...

  • Page 124

    Figure 11.2.2.2 Flow example after receiving Self-ID packet. Rev.1.0 <Device> Prepare for reading received data Read one word of received data and increment the read pointer Of receive buffer. Receive Remove busy (04h) instruction. FIFO remote mode for receiving completed. recv busy bit=0 MB86617A Fujitsu VLSI...

  • Page 125

    Note2: If the transmitting length is below the digit of quadret, write “0” there up to quadret unit. Note3: The device can automatically attaches CRC code. Rev.1.0 <Host> MB86617A <Device> Write data for 1 word for Asynchronous transmit buffer and increment the write pointer.

  • Page 126

    After the transfer of DATA_END, release bus and wait Asynchronous packet receiving. Acknowledge received? Store receive Acknowledge packet in receive Acknowledge indication register. Report Asynchronous packet send (INT17) interrupt (assert XINT). Report Acknowledge missing (INT20) interrupt (assert XINT). MB86617A Lost Fujitsu VLSI...

  • Page 127

    LSI S pecification MB86617A 11.4. Asynchronous Packet Receiving The example of control flow for receiving Asynchronous packet is shown below. Rev.1.0 Fujitsu VLSI...

  • Page 128

    Store Asynchronous packet into Async hronous receive buffer. Transmit Acknowledge packet Receive buffer=full Report Asynchronous Receive FIFO full (INT16) interrupt(assert XINT). Report Asynchronous packet receive (INT9) interrupt(assert XINT). recv busy bit=1 Packet receiving process completed MB86617A ‘0’ Fujitsu VLSI...

  • Page 129

    Note1: If the length of received data is below quadret digid, it is stored by quadret unit????. Note2: CRC code is not included in the data. Rev.1.0 MB86617A <Device> Prepare for reading received data. Read 1 word of received data and increment read pointer of receive buffer.

  • Page 130

    LSI S pecification MB86617A 11.5. Isochronous Packet Transmitting The example of control flow for transmitting Isochronous packet is shown below. Rev.1.0 Fujitsu VLSI...

  • Page 131

    CP LSI and store it in FIFO at Bridge. Isocycle Arbitration procedure Arbitration result Transmit Late evaluation Transmit Late Report Transmit late occurred (INT32) interrupt(assert XINT). Discard source packet and transmit empty packet. Connect source packet according to register setting and transmit. MB86617A Lost Fujitsu VLSI...

  • Page 132

    Set at Bch transmitting. TXSTB=1, TFB Rev.1.0 Data MPEG-TS DBSA=09h, FNA=2h TXFMTA=21h, TXCHA(Iso channel No.) DBSB=09h, FNB=2h TXFMTB=21h, TXCHB(Iso channel No.) Set at Ach transmitting. TXSTA=1, TFA, TXFMTA=1, IDSIZEA=1(DSS130) Set at Bch transmitting. TXSTB=1, TFB, TXFMTB=1, IDSIZEB=1(DSS130) MB86617A Fujitsu VLSI...

  • Page 133

    CP LSI and store it in FIFO at TSPIF. Receive Late evaluation Receive Late Report Receive late occurred(INT30) interrupt(assert XINT). Discard source packet. Output source packet from the TSPIF port when the value of source packet header equals to the value of cycle timer. MB86617A Fujitsu VLSI...

  • Page 134

    Set criteria for Late packet (Bch). Ach received : RXSTA=1h, RXCHA(Iso channel No.) Bch received : RXSTB=1h, RXCHB(Iso channel No.) Rev.1.0 Data DSSEN=1, DVEN=1, TV1A,TV1B,TV2A,TV2B according to Ch received and according to Ch received and port. port. MB86617A TV1A,TV1B,TV2A,TV2B Fujitsu VLSI...

  • Page 135

    LSI S pecification MB86617A Chapter 12 System Configuration This chapter explains the system configuration of this chip. 12.1. Recommended Connection for 1934 Port (for one port) 12.2. Recommended Connection for Cable Power Supply 12.3. Recommended Connection for Build-in PLL Loop Filter 12.4.

  • Page 136

    LSI S pecification MB86617A 12.1. Recommended Connection for 1934 Port (for one port) The example of recommended connection of 1934 port terminal for one port is shown below. 5.1k 250pF 5.1k ア1% Recommended connection for 1934 port (for one port) Figure 12.1...

  • Page 137

    Recommended Connection for Cable Power Supply 12.2 The example of recommended connection of cable power supply for 1394 cable is shown below. 2.2uF Figure 12.2 Rev.1.0 510K Recommended connection for cable power supply MB86617A Power Cable (max 33V) Fujitsu VLSI...

  • Page 138

    LSI S pecification 12.3. Recommended Connection for Build-in PLL Loop Filter recommended connection for build-in PLL loop filter is shown below. The example of Figure 12.3 Rev.1.0 3300pF 5% Recommended connection for build-in PLL loop filter MB86617A 5.1K Fujitsu VLSI...

  • Page 139

    The example of No outside resistance is needed because the feedback resistance is built -in.??? Figure 12.4 Rev.1.0 20pF Configuration of feedback circuit at crystal oscillator MB86617A 20pF Fujitsu VLSI...

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