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CHAPTER 16 DMA CONTROLLER (DMAC)
Figure 16.3-6 Example of the Timing for Negating the DREQ Pin Input for 2-Cycle Transfer from an
External bus clock
CS0
CS1
AS
RD
WRn
DREQn
DACKn
Negate the range of DERQ pin input indicated with the arrow. If you set the negation timing later than
the circular mark
•
For transfer from internal to external circuits:
Use the DREQ negation sense timing so that it is placed prior to the write strobe negation
timing by a single cycle or more. There are following measures for achieving this:
- Make the DREQ negation timing by a single cycle or more with the adjustment on the
external I/O side or external glue logic side.
- Increase the wait value from the current value by a single cycle or more by using the auto
wait capability in the external bus controller provided with the FR.
If DREQ is negated after the period when DACK and WR are at the L level, the next transfer
may be executed.
366
External Circuit to an Internal Circuit
, an extra round of signal may be transferred.
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