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CHAPTER 16 DMA CONTROLLER (DMAC)
[bit23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification
This bit controls reloading of the transfer count register for the corresponding channel.
If reloading of the counter is enabled by this bit, the count register value is restored to its initial
value after transfer is completed, then DMAC stops and starts waiting for a new transfer
request (an activation request by STRG or IS setting). If this bit is 1, the DENB bit is not
cleared.
DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly
stopped.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation,
operation stops after the transfer is completed even if reload is specified in the address
register. The DENB bit is also cleared in this case.
Table 16.2-10 shows the specification of transfer counter register reloading.
Table 16.2-10 Specification of Transfer Counter Register Reloading
DTCR
0
1
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[bit22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload
This bit controls reloading of the transfer source address register for the corresponding
channel.
If this bit enables the reload operation, the transfer source address register value is restored to
its initial value after the transfer is completed.
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation,
operation stops after the transfer is completed even if reload is specified in the address
register. The address register value also stops in this case while the initial value is being
reloaded.
If this bit disables the reload operation, the address register value when the transfer is
completed is the address to be accessed next to the final address. When address increment is
specified, the next address is an incremented address.
Table 16.2-11 shows the specification of transfer source address register reloading.
Table 16.2-11 Specification of Transfer Source Address Register Reloading
SADR
0
1
•
When reset: Initialized to 0.
•
This bit is readable and writable.
332
Disables transfer count register reloading (initial value)
Enables transfer count register reloading.
Disables transfer source address register reloading. (initial value)
Enables transfer source address register reloading.
Function
specification
Function
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