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CHAPTER 14 UART
❍ Send operation in modes 0, 1, and 2
TDRE is cleared when data is written to the SODR register. This bit is set when data is
transferred to the internal shift register and the next data can be written, causing an interrupt
request to be generated for the CPU. If 0 is written to TXE of the SCR register (as well as RXE in
mode 2) during a send operation, TDRE of the SSR register is set to 1, disabling the UART send
operation after the transmission shiftier stops. The device sends data written to the SODR
register before transmission stops after 0 is written to the TXE of the SCR register (as well as
RXE in mode 2) during the send operation.
Figure 14.2-11 shows the timing for setting TDRE in Modes 0 and 1. Figure 14.2-12 shows the
timing for setting TDRE in Mode 2.
Writing to SODR
ST: Start bit, D0 to D7: Data bits
SP: Stop bit, A/D: Address/data multiplexer
Writing to SODR
■ Precautions on Usage
Writing to the SODR register starts communication. Even for receive only, dummy send data
must be written to the SODR register.
Set the operating mode while operation is stopped. Data send and received while the operating
mode is being set is unpredictable.
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Figure 14.2-11 Timing for Setting TDRE (Modes 0 and 1)
TDRE
SO interrupt
SO output
Figure 14.2-12 Timing for Setting TDRE (Mode 2)
TDRE
SO interrupt
SO output
Interrupt request to CPU
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
Interrupt request to CPU
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 to D7: Data bits
A/D
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