Fujitsu MB91319 Series Hardware Manual page 459

Figure 17.4-1 Timing Diagram for BULK IN Transfer (Writing by CPU and Reading by USB)
FIFO (a)
Writing by
CPU
1)
FIFO (b)
IRQ
1)
PACKET N
2)
PACKET N+1
3)
4)
LAST PACKET
5)
6)
7)
Shading indicates
existence of data.
PACKET N PACKET N+1
Reading by Writing by
USB CPU
2)
ACK1
Writing by Reading by
CPU USB
3) 4)
* After the last data has been written, no interrupt occurs until transmission
of the last packet ends. The end of transmission of the last packet must be
determined from an interrupt because it cannot be determined from polling of
the LSTD2 bit of the CONT10 register.
CPU bus side
FIFO (a)
FIFO (b)
FIFO (a)
FIFO (b)
FIFO (a)
Writing disabled
FIFO (b)
Writing enabled
FIFO (a)
FIFO (b)
FIFO (a)
Writing disabled
FIFO (b)
FIFO (a)
Writing enabled
FIFO (b)
CHAPTER 17 USB FUNCTION
PACKET N+1 LAST PACKET
Reading by
USB
7)
5) 6)
Reading by
USB
NACK1
ACK2
*
USB bus side
Transmission disabled
Transmission enabled
PACKET N
PACKET N+1
PACKET N+1
PACKET N+1
ACK1
NACK
ACK2
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