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Table A-1 I/O Map (1 / 9)
Address
+0
000000
H
|
-
00000F
H
PDR0[R/W]
000010
H
XXXXXXXX
PDR4[R/W]
000014
H
XXXXXXXX
PDR8[R/W]
000018
H
XXXXXXXX
PDRC[R/W]
00001C
H
XXXXXXXX
ADCTH[R/W]
000020
H
00000000
000024
H
XXXXXX00_00000000
000028
H
XXXXXX00_00000000
00002C
H
XXXXXX00_00000000
000030
H
XXXXXX00_00000000
000034
-
H
000038
-
H
00003C
-
H
EIRR [R/W]
000040
H
00000000
DICR [R/W]
000044
H
-------0
000048
H
XXXXXXXX XXXXXXXX
00004C
H
000050
H
XXXXXXXX XXXXXXXX
000054
H
000058
H
XXXXXXXX XXXXXXXX
00005C
H
SSR0 [R/W]
000060
H
00001-00
UTIM0 [R] (UTIMR0 [W])
000064
H
00000000 00000000
SSR1 [R/W]
000068
H
00001000
Register
+1
-
PDR1[R/W]
XXXXXXXX
PDR5[R/W]
XXXXXXXX
PDR9[R/W]
XXXXXXXX
-
ADCTL[R/W]
00000000
ADAT0[R]
ADAT2[R]
ADAT4[R]
ADAT6[R]
-
-
-
ENIR [R/W]
00000000
HRCL [R/W]
0--11111
TMRLR0 [W]
--------
TMRLR1 [W]
--------
TMRLR2 [W]
--------
SIDR0[R]/SODR0[W]
XXXXXXXX
SIDR1[R]/SODR1[W]
XXXXXXXX
+2
-
PDR2[R/W]
PDR3[R/W]
XXXXXXXX
XXXXXXXX
PDR7[R/W]
-
--XXXXXX
PDRA[R/W]
PDRB[R/W]
-----XXX
XXXXXXXX
-
ADCH[R/W]
00000000_00000000
ADAT1[R]
XXXXXX00_00000000
ADAT3[R]
XXXXXX00_00000000
ADAT5[R]
XXXXXX00_00000000
ADAT7[R]
XXXXXX00_00000000
-
-
-
ELVR [R/W]
00000000
--------
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSR0 [R/W]
----0000 00000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSR1 [R/W]
----0000 00000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSR2 [R/W]
----0000 00000000
SCR0 [R/W]
SMR0 [R/W]
00000100
00--0---
DRCL0
UTIMC0 [R/W]
*3
0--00001
--------
SCR1 [R/W]
SMR1 [R/W]
00000100
00--0---
APPENDIX A I/O Map
Block
+3
-
Reserved
R-bus
Port Data Register
-
10bit A/D converter
-
-
Reserved
-
Ext int
DLYI/I-unit
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0
U-TIMER 0
UART1
671
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