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CHAPTER 3 CPU AND CONTROL UNITS
Reference:
For details on using software reset of synchronous mode, see restrictions of bit7: SYNCR bit of TBCR (time
base counter control register).
■ Watchdog Reset
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5
is written to the time base counter clear register (CTBR) within the cycle specified in bit9 and bit8
(WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs.
A watchdog reset request is a settings initialization reset (INIT) request. If, after the request is
accepted, a settings initialization reset (INIT) occurs or an operation initialization reset (RST)
occurs, the watchdog reset request is cleared.
If a settings initialization reset (INIT) is generated due to a watchdog reset request, bit13 (WDOG
bit) in the reset source register (RSRR) is set.
Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request, the
oscillation stabilization wait time is not initialized.
•
Reset source:
•
Source of clearing:
•
Reset level:
•
Corresponding flag:
70
Setting cycle of the watchdog timer elapses
Generation of a settings initialization reset (INIT) or an operation
initialization reset (RST)
Settings initialization reset (INIT)
bit13 (WDOG)
/5A
H
H
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