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CHAPTER 3 CPU AND CONTROL UNITS
3.8.5
Multiple EIT Processing
If multiple EIT causes occur at the same time, the CPU repeats the operation of
selecting and accepting one of the EIT causes, executing the EIT sequence, and then
detecting EIT causes again. If there are no more EIT causes be accepted while the CPU
is detecting EIT causes, the CPU executes the handler instruction of the last accepted
EIT cause. As a result, the order of executing handlers for multiple EIT causes that
occur at the same time is determined according to the following two elements:
• Priority of EIT causes to be accepted
• How other causes can be masked when one cause is accepted
■ Priority of EIT Causes To Be Accepted
The priority of EIT causes to be accepted is the order of causes for which the EIT sequence is to
be executed (that is, saving the PS and PC, updating the PC, and masking other causes, if
required). The handler of a cause accepted earlier is not necessarily executed earlier.
Table 3.8-4 lists the acceptance priority of EIT causes.
Table 3.8-4 Priority of EIT Causes to Be Accepted and Masking of Other Causes
Priority of
acceptance
*: The priority is 6 only if the INTE instruction and the NMI for emulators occur at the same time.
(The NMI for emulators is used for breaks due to data access).
58
1
Reset
2
Undefined instruction exception
3
INT instruction
4
No-coprocessor trap
5
User interrupt
6
NMI (for users)
7
(INTE instruction)
8
NMI (for emulators)
9
Step trace trap
10
INTE instruction
Cause
Other causes are abandoned.
Canceled
I flag=0
Coprocessor error trap
ILM=level of cause accepted
ILM=15
ILM=4
ILM=4
ILM=4
ILM=4
Masking of other causes
*
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