Table of Contents
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Display Control Command
Display Control Command List
List of Display Control Commands
Setup Stage of Control Transfer
(Class and Vendor Commands and Some Standard
Commands[Get_Descriptor, Set_Descriptor, and
Synch_Frame])
Status Stage of Control Transfer
(Class and Vendor Commands and Some Standard
Commands[Get_Descriptor, Set_Descriptor, and
Synch_Frame])
Command Sequence
............................................ 644
Command Sequence
Communication
Communication Error that Causes No Error
........................................ 273
End of Communication
Start of Communication
Compare Instructions
........................................... 705
Compare Instructions
Connection Diagram
........................................... 625
Connection Diagram
CONT
............................................................ 394
CONT1
.......................................................... 405
CONT10
............................................................ 396
CONT2
............................................................ 398
CONT3
............................................................ 399
CONT4
............................................................ 400
CONT5
............................................................ 401
CONT6
............................................................ 402
CONT7
............................................................ 403
CONT8
............................................................ 404
CONT9
Control Status Register
Bit Configuration of the Control Status Register (TMCSR)
.......................................................... 140
Bit Functions of the Control Status Register (TMCSR)
.......................................................... 140
Control/Status Register B (DMACB0 to 4)
Register Configurations of Control Status Registers
(PCNH and PCNL)
Control/Status Registers A (DMACA0 to 4)
Coprocessor
.......................................... 63
Coprocessor Error Trap
............................................. 63
No-coprocessor Trap
Coprocessor Control Instructions
Coprocessor Control Instructions
Correction
Field Correction Control
CPU
.............................................. 80
CPU Clock (CLKB)
Example of Controlling Reception at CPU Access
Example of Controlling Transmission at CPU Access
.......................................................... 429
............................................................... 2
FR CPU
Timing Diagram for BULK IN Transfer
(Writing by CPU and Reading by USB)
Timing Diagram for BULK OUT Transfer
(Reading by CPU and Writing by USB)
................................... 609
.............................. 610
......................... 570
..................................... 411
..................................... 412
.............. 313
....................................... 273
............... 329
................................ 156
............. 324
............................ 720
....................................... 555
...... 427
...... 436
...... 438
CPU IN Transfer
.................................................416
CPU IN Transfer
CPU Mode
Configuration of Flash Control/Status Register (FLCR)
.........................................638
(CPU Mode)
CPU OUT Transfer
..............................................418
CPU OUT Transfer
CTBR
Time Base Counter Clear Register (CTBR)
D
D+ Terminating Resister
Controlling the D+ Terminating Resister on the Board
..........................................................441
DACK
Pin Function of the DACK, and DEOP, and DREQ Pins
..........................................................340
Timing of DACK Pin Output
Data Access
.........................................................44
Data Access
Data Direction Registers
Configuration of the Data Direction Registers (DDR)
..........................................................131
Data Length
Data Length (Data Width)
Data Register
...........................................305
Data Register (IDAR)
Data Stage
Control Transfer (Data Stage) and BULK OUT Transfer
..........................................................413
Control Transfer (Data Stage), Bulk Transfer, or
INTERRUPT IN Transfer
Data Width
Data Length (Data Width)
DDR
Configuration of the Data Direction Registers (DDR)
..........................................................131
Default Status
USB Function Macro Program Operation in the Default
..................................................444
Status
Delay
Normal Branch (No Delay) Instructions
Delay Slot
Branch Instruction with Delay Slot
Branch Instruction without Delay Slot
Precaution on Delay Slot
Delayed Branch Instructions
Delayed Branch Instructions
Delayed Branch Macro Instructions
20-Bit Delayed Branch Macro Instructions
32-Bit Delayed Branch Macro Instructions
Delayed Interrupt Control Register
Delayed Interrupt Control Register
(DICR: Delayed Interrupt Control Register)
..........................................................229
.................91
.................................368
.....................................354
........................414
.....................................354
....................712
............................46
........................48
.........................................63
..................................713
................716
................718
727
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