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CHAPTER 3 CPU AND CONTROL UNITS
■ Clock Source Control Register (CLKR)
Figure 3.11-6 shows the configuration of the clock source control register (CLKR) bits.
Figure 3.11-6 Configuration of Clock Source Control Register (CLKR) Bits
Address: 00000484
Initial value (INIT)
Initial value (RST)
The clock source control register is used to select the clock source that will be used as the base
clock of the system and controls the PLL. Use this register to select one of three clock sources
(the MB91319 supports only two of these). This register also enables the main PLL and each of
the sub-PLLs and selects the multiply-by rate for them.
[bit15] PLL2S0 (PLL2 ratio Select 0)
This bit is the multiply-by rate selection bit for the subclock.
Select one of the two multiply-by rates for the subclock.
Always write 0 to this bit for the MB91319.
0
1
•
This bit is initialized to 0 by a reset (INIT).
•
This bit is readable and writable.
[bit14 to bit12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2-0)
These bits are the multiply-by selection bits for the main PLL. Select one of the eight multiply-
by rates (the MB91319 supports only four of these) shown in Table 3.11-2.
Note:
Rewriting of this bit is disabled while the main PLL is selected as the clock source. The upper-limit
frequency for operation is 40 MHz.
exceeding this limit.
92
bit
15
14
PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0
H
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
x
x
Multiply-by rate setting 1 (initial value)
Multiply-by rate setting 1
Do not set a multiply-by rate that results in a frequency
13
12
11
10
0
0
0
0
x
x
x
x
9
8
0
0
x
x
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