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■ Block Diagram
Figure 3.14-1 Block Diagram of the Main Clock Oscillation Stabilization Wait Timer
Main clock oscillation
stabilization wait
timer counter
F
Main clock oscillation
stabilization wait
timer interrupt request
Main clock oscillation
stabilization wait timer
control register (OSCR)
❍ Main clock oscillation stabilization wait timer
The main clock oscillation stabilization wait timer is a 32-bit incremental counter that uses the
main clock source oscillation as the count clock.
❍ Counter clear circuit
The counter clear circuit clears the counter not only when the WCL bit of the OSCR register is set
to 0 but also when a reset (INIT) request is generated.
❍ Interval timer selector
The interval timer selector selects one of the three frequency-divide outputs of the main clock
oscillation stabilization wait timer counter for the interval timer. The trailing edge of the selected
frequency-divide output becomes an interrupt source.
❍ Main clock oscillation stabilization wait timer control register (OSCR)
The main clock oscillation stabilization wait timer control register is used to select the interval
time, clear the counter, control interrupts, and check counter status.
0
1
1
2
2
2
CL
WIF
CHAPTER 3 CPU AND CONTROL UNITS
2
3
4
5
6
7
3
4
5
6
7
8
2
2
2
2
2
2
Interval
timer
selector
WIE
F
: Main clock source oscillation
CL
The numbers in parentheses indicate the intervals
when the main clock source oscillation
frequency is 10 MHz.
8
11
16
9
1 2
1 7
2
2
2
(410µs)
(13.1ms)
(839ms)
Reset
Counter
(INIT)
clear circuit
WS1
WS0
22
2 3
2
WCL
121
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