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CHAPTER 3 CPU AND CONTROL UNITS
1
INTX pin = 0 (INIT)
2
INTX pin = 1 (clearance of INIT state)
3
End of oscillation stabilization wait time
4
Release from reset (RST) state
5
Software reset (RST)
6
Entry to sleep state (writing of instruction)
7
Entry to stop state (writing of instruction)
8
Interrupt
9
External interrupt not requiring a clock
10
Switching from main clock to subclock
(writing of instruction)
11
Switching from subclock to main clock
(writing of instruction)
12
Watchdog timer reset (INT)
13
Entry to subclock sleep state
(writing of instruction)
Notes:
• To switch the clock source between the main clock and subclock, change the status of bit1 and
bit0 (CLKS1 and CLKS0 bits) of the clock source register (CLKR) in the RUN state after oscillation
of the switch-destination clock has been stabilized.
• To stop a circuit other than the watch timer in the watch state, set bit1 (OSCD2 bit) of the standby
control register (STCR) to 0 in the subclock RUN state then change to stop mode.
106
Figure 3.12-1 Transition of Device States
Main clock mode
1
Main clock stop
9
1
Oscillation
stabilization
3
wait RUN
1
Main clock sleep
8
Subclock mode
1
8
Subclock sleep
13
3
1
Main clock sleep
9
1
Subclock stop
(watch state)
Highest
Power-on
1
Lowest
Setting
initialization
reset (INIT)
2
Main clock
oscillation
1
stabilization wait reset
3
Program reset
(RST)
1
4
7
5
12
6
Main clock RUN
1
10
11
12
Subclock RUN
1
7
5
4
Program reset
(RST)
1
Priority of state transition
requests
Settings initialization reset
(INIT) request
End of oscillation stabilization
wait time
Operation initialization reset
(RST) request
Interrupt request
Stop mode request
Sleep mode request
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