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CHAPTER 3 CPU AND CONTROL UNITS
■ Operation of Step Trace Trap
Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then
occur every time an instruction is executed.
[Step trace trap detection conditions]
T flag =1
There is no delayed branch instruction.
A processing routine other than the INTE instruction or a step trace trap is in progress.
If the above conditions are met, a break occurs between instruction operations.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of next instruction → (SSP)
5. "00100" → ILM
6. "0" → S flag
7. (TBR+3CC
Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIT
occurs due to the INTE instruction.
A trap occurs in the instruction following the one in which the T flag has been set.
■ Operation of Undefined Instruction Exception
If, during instruction decode, an undefined instruction is detected, an undefined instruction
exception occurs.
An undefined instruction exception is detected under the following conditions:
•
An undefined instruction is detected during instruction decode.
•
The instruction is not located in the delay slot (it does not immediately follow the delay branch
instruction).
If the above conditions are met, an undefined instruction exception and a break occur.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. PC → (SSP)
5. "0" → S flag
6. (TBR+3C4
The PC value to be saved is the address of an instruction that detected an undefined instruction
exception.
62
) → PC
H
) → PC
H
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