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CHAPTER 17 USB FUNCTION
The operation shown in the figure is explained below.
1. Data is written from the CPU to FIFO buffer (a) for transmission.
2. When FIFO buffer (a) (64 bytes) becomes full and the transfer enable bit (BFOK) is set,
transmission to the USB is started. At the same time, FIFO buffer (b) becomes visible from
the CPU and the next send data can be written to FIFO buffer (b).
3. When data writing to FIFO buffer (b) ends, the transfer enable bit (BFOK) is set. At the same
time, FIFO buffer (a) becomes visible from the CPU. However, data writing from the CPU to
FIFO buffer (a) cannot be started because data transmission from FIFO buffer (a) to the USB
is not completed.
If data transmission from FIFO buffer (a) ends without an error, an ACK signal (ACK1) is
returned.
4. When the ACK signal (ACK1) is returned, FIFO buffer (a) enters the write-enabled status. The
next data is written from the CPU.
Transmission to the USB is started because transmission-enabled data has already been
written to FIFO buffer (b).
5. When data writing to FIFO buffer (a) ends, the transfer enable bit (BFOK) is set. At the same
time, FIFO buffer (b) becomes visible from the CPU. However, data writing from the CPU to
FIFO buffer (b) cannot be started because data transmission from FIFO buffer (b) to the USB
is not completed.
If data transmission from FIFO buffer (b) ends with an error, a NACK signal is returned.
6. If a NACK signal is returned, data is retransmitted from FIFO buffer (b) to the USB. Data
writing from the CPU to FIFO buffer (b) cannot be started because data transmission from
FIFO buffer (b) to the USB is not completed.
If data retransmission from FIFO buffer (b) ends without an error, an ACK signal (ACK2) is
returned.
7. When the ACK signal (ACK2) is returned, FIFO buffer (b) enters the write-enabled status.
However, no interrupt occurs until transmission of the last packet is completed.
■ Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB)
Figure 17.4-2 shows the timing diagram for double-buffer operation during BULK OUT transfer
and the operation diagram.
In the example below, the MNACK bit of the CONT8 register (control register) is set so that an
IRQ signal is not asserted by NACK.
438
FIFO buffer (b) becomes visible from the USB.
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