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■ Operation of The Watch Timer
Figure 3.13-3 shows the counter states at start of watch timer, switching to the subclock, and
transition to stop mode during operation with the subclock.
7FFF
H
Value of counter
4000
H
- Timer clearance (WCL bit = 1)
(other than 0)
- Timer interval selection
(WS1 and WS0 bits = 11
- Start of subclock oscillation
(PLL2EN bit of CLKR = 1)
WIF
Clock source
Clock mode
- Change of interval time
(WS1 and WS0 bits = 10
- Switching from main clock to subclock
■ Precautions for Using the Watch Timer
•
Use the oscillation stabilization wait time as a reference value because the oscillation cycle is
unstable immediately after oscillation is started.
•
No timer interrupt is generated while subclock oscillation is stopped because the watch timer
is stopped when subclock oscillation is stopped. Do not stop subclock oscillation if it is
necessary to use the watch timer for processing.
•
If a WIF setting request occurs at the same time as a zero-clearance request from the CPU,
the WIF setting request has priority and the zero-clearance request is ignored.
Figure 3.13-3 Counter States at Transition to Stop Mode
Subclock oscillation
Interval time
stabilization wait time
)
Cleared by interrupt routine
B
Main clock
RUN
)
B
CHAPTER 3 CPU AND CONTROL UNITS
Subclock
Instruction to enter stop mode
* When the OSCD2 bit of STCR is set to 0 (oscillation is
not stopped in stop mode)
*
Stop
RUN
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