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CHAPTER 3 CPU AND CONTROL UNITS
[bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3-0)
These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set the
clock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP). The values
written to these bits determine the divide-by rate (clock frequency) of the peripheral circuit and
the peripheral bus clock in relation to the base clock, which can be selected from the 16 types
shown in Table 3.11-6.
The upper-limit frequency for operation is 20 MHz. Do not set a divide-by rate that results in a
frequency exceeding this limit.
Table 3.11-6 Clock Divide-by Rate (Peripheral Clock ) Settings
P3
P2
P1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
...
...
...
1
1
1
φ: Frequency of the system base clock
•
These bits are initialized to 0011 by a reset (INIT).
•
These bits are readable and writable.
■ Base Clock Division Setting Register 1 (DIVR1)
Figure 3.11-8 shows the configuration of the Base Clock Division Setting Register 1 (DIVR1) bits.
Figure 3.11-8 Configuration of Base Clock Division Setting Register 1 (DIVR1) Bits
Address: 00000487
Initial value (INIT)
Initial value (RST)
Base clock division setting register 1 controls the divide-by rate of an internal clock in relation to
the base clock.
This register sets the divide-by rate for the external extended bus interface clock (CLKT).
An upper-limit frequency for the operation is set for each clock. If the combination of source clock
selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding
this upper-limit frequency, operation is unpredictable. (Be extremely careful of the order in which
you change the settings when selecting the source clock.)
96
P0
Clock divide-by rate
φ
0
φ × 2 (divided by 2)
1
φ × 3 (divided by 3)
0
φ × 4 (divided by 4)
1
φ × 5 (divided by 5)
0
φ × 6 (divided by 6)
1
φ × 7 (divided by 7)
0
φ × 8 (divided by 8)
1
...
...
φ × 16 (divided by 16)
1
bit
7
6
T3
T2
H
R/W
R/W
0
0
x
x
Clock frequency: if the source oscillation
is 10 [MHz] and the PLL is multiplied by 4
10 [MHz] (initial value)
5
4
3
2
T1
T0
-
-
R/W
R/W
R/W
R/W
0
0
0
0
x
x
x
x
40 [MHz]
20 [MHz]
13.3 [MHz]
8 [MHz]
6.67 [MHz]
5.71 [MHz]
5 [MHz]
...
2.5 [MHz]
1
0
-
-
R/W
R/W
0
0
x
x
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