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CHAPTER 3 CPU AND CONTROL UNITS
3.10.4
Oscillation Stabilization Wait Time
If a device returns from the state in which the original oscillation was or may have been
stopped, the device automatically enters the oscillation stabilization wait state. This
function prevents the use of oscillator output after starting before oscillation has
stabilized.
For the oscillation stabilization wait time, neither an internal nor an external clock is
supplied; only the built-in time base counter runs until the stabilization wait time set in
the standby control register (STCR) has elapsed.
This section describes the oscillation stabilization wait operation.
■ Sources of an Oscillation Stabilization Wait
The following lists sources of an oscillation stabilization wait.
❍ Clearing of a settings initialization reset (INIT)
The device enters the oscillation stabilization wait state if a settings initialization reset (INIT) is
cleared for a variety of reasons.
When the oscillation stabilization wait time has elapsed, the device enters the operation
initialization reset (RST) state.
❍ Returning from stop mode
The device enters the oscillation stabilization wait state immediately after stop mode is cleared.
However, if it is cleared by a settings initialization reset (INIT) request, the device enters the
settings initialization reset (INIT) state.
cleared, the device enters the oscillation stabilization wait state.
When the oscillation stabilization wait time has elapsed, the device enters the state
corresponding to the source that cleared stop mode:
•
Return due to input of a valid external interrupt request (including NMI):
•
Return due to a settings initialization reset (INIT) request:
•
Return due to an operation initialization reset (RST) request:
❍ Returning from an abnormal state when PLL is selected
If, while the device is operating with PLL as the source clock, an abnormal condition* occurs in
PLL control, the device automatically enters an oscillation stabilization wait to assure the PLL lock
time.
When the oscillation stabilization wait time has elapsed, the device enters the normal operating
state.
*: The multiply-by rate is changed while PLL is working, or an incorrect bit such as a bit
equivalent to PLL operation enable bit is generated.
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The device enters the normal operating state.
The device enters the operation initialization reset (RST) state.
The device enters the operation initialization reset (RST) state.
Then, after the settings initialization reset (INIT) is
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