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CHAPTER 9 INTERRUPT CONTROLLER
9.2.2
Hold Request Cancellation Request Level Setting
Register (HRCL)
The hold request cancellation request level setting register (HRCL) is a level setting
register used to generate a hold request cancellation request.
■ Hold Request Cancellation Request Level Setting Register (HRCL)
Figure 9.2-3 shows the bit configuration of the hold request cancellation request level setting
register (HRCL).
Figure 9.2-3 Bit Configuration of the Hold Request Cancellation Request Level Setting Register (HRCL)
bit
Address: 00000045
[bit7] MHALTI
This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets this
bit to 1. Write 0 to this bit to clear it. At the end of an NMI routine, clear this bit the same way it
would be cleared in a normal interrupt routine.
[bit4 to bit0] LVL4 to LVL0
This bit sets the interrupt level used to issue a hold request cancellation request to the bus
master.
If an interrupt request with a higher level than the level defined in the HRCL register occurs, a
hold request cancellation request is issued to the bus master.
The LVL4 bit is always 1; 0 cannot be written to this bit.
210
7
6
5
MHALTI
--
--
H
R/W
4
3
2
1
LVL4 LVL3 LVL2 LVL1 LVL0
R
R/W
R/W R/W
0
Initial value
R/W
0--11111
B
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