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■ Other Operation
Channels 0 and 1 of the 16-bit reload timer support the start of DMA transfer occurring due to
interrupt request signals.
The DMA controller clears the interrupt flag of the reload timer as soon as a transfer request is
accepted.
●
Operating States of the Counter
The counter state is determined by the CNTE bit of the control status register (TMCSR) and the
WAIT signal, which is an internal signal. The states that can be set include the stop state, when
CNTE=0 and WAIT=1 (STOP state); the startup trigger wait state, when CNTE=1 and WAIT=1
(WAIT status); and the operation state, when CNTE=1 and WAIT=0 (RUN state).
Figure 5.3-6 shows the state transitions.
Reset
CNTE="0"
CNTE=1, WAIT=1
WAIT
T1: Only trigger input enabled
T0: Initial value output
Counter: Holds the value
when it stops; undefined just
after reset and until data is
loaded
Trigger from TIN
Figure 5.3-6 Status Transitions of Counter
STOP
CNTE=0, WAIT=1
T1: Input disabled
T0: General-purpose port
Counter: Holds the value
when it stops; undefined
just after reset
CNTE="1"
CNTE="1"
TRG="1"
TRG="0"
RELD UF
TRG="1"
LOAD
CNTE=1, WAIT=0
Loads contents of reload
register into counter.
CHAPTER 5 16-BIT RELOAD TIMER
State transition due to hardware
State transition due to register access
CNTE="0"
CNTE=1, WAIT=0
RUN
T1: Serves as T1
T0: Serves as T0
Counter: Running
TRG="1"
RELD UF
Load completed
149
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