Block Diagram Of Clock Generation Controller - Fujitsu MB91319 Series Hardware Manual

3.11.5

Block Diagram of Clock Generation Controller

This section provides a block diagram of the clock generation controller.
The detailed description of register in the figure refers to 8 Detailed explanation for
register of clock generation controller.
■ Block Diagram
Figure 3.11-1 shows a block diagram of the clock generation controller.
Main clock
oscillator
stabilization
wait timer
(for subclock
selection)
X0
Oscilla-
tion
X1
circuit
X0A
Oscilla-
tion
circuit
X1A
Watch timer
Internal interrupt
Internal reset
INIT pin
Figure 3.11-1 Block Diagram of Clock Generation Controller
Peripheral circuit operation stop control register
[Clock generator]
DIVR0,1 registers
CLKR register
PLL
Main
clock
1/2
Sub
clock
[Stop and sleep controller]
STCR register
[Reset source circuit]
RSRR register
[Watchdog controller]
CTBR register
TBCR register
Interrupt enable
CHAPTER 3 CPU AND CONTROL UNITS
CPU clock division
Selector
Peripheral clock division
Selector
External bus clock division
Selector
Status
transition
control
circuit Reset
occurrence F/F
Reset
occurrence F/F
Watchdog F/F
Time base counter
Selector
Overflow detection F/F
CPU clock
Peripheral clock
External bus clock
Stop status
Sleep status
Internal reset (RST)
Internal reset (INIT)
Counter clock
Time base timer
interrupt reques
83