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Synchronization Control
Synchronization Control (Vertical Enlargement Control)
.......................................................... 561
Synchronous
Example of Horizontal Synchronous Operation
Horizontal Synchronous Operation
Synchronous Reset
Synchronous Reset Operation
System Configuration
System Configuration of AF220/AF210/AF120/AF110
Flash Micro-controller Programmer
System Stack Pointer
System Stack Pointer (SSP)
T
Table Base Register
Table Base Register (TBR)
TBCR
Time Base Counter Control Register (TBCR)
TBR
Table Base Register (TBR)
Temporary Sector Erase Stop
Temporary Sector Erase Stop
Temporary Stopping
............................................ 359
Temporary Stopping
Time Base Counter
............................................. 100
Time Base Counter
Time Base Counter Clear Register
Time Base Counter Clear Register (CTBR)
Time Base Counter Control Register
Time Base Counter Control Register (TBCR)
Timer Compare Data Register
Timer Compare Data Register (TxDRR)
Timer Setting Register
Timer Setting Register (TxTCR)
Timing Chart
Interrupt Resources and Timing Chart
One-shot Mode Timing Charts
PWM Mode Timing Chart
TMCSR
Bit Configuration of the Control Status Register (TMCSR)
.......................................................... 140
Bit Functions of the Control Status Register (TMCSR)
.......................................................... 140
TMODE
........................................................... 181
TMODE
TMR
Bit Configuration of the 16-bit Timer Register (TMR)
.......................................................... 143
TMRLR
Bit Configuration of the 16-bit Reload Register (TMRLR)
.......................................................... 144
Tool Reset Pins
......................................... 24
Tool Reset Pins (TRST)
......... 551
......................... 551
.................................. 74
........... 667
.................................... 53
..................................... 54
.............. 88
..................................... 54
................................ 660
................. 91
.............. 88
.................. 179
............................ 176
..................... 166
............................... 164
.................................... 162
Trace Trap
Operation of Step Trace Trap
Transfer
....................................................370
Block Transfer
.........................................346
Burst 2-Cycle Transfer
...........................................347
Burst Fly-by Transfer
....................................................371
Burst Transfer
Control Transfer (Data Stage) and BULK OUT Transfer
..........................................................413
Control Transfer (Data Stage), Bulk Transfer, or
INTERRUPT IN Transfer
.................................................416
CPU IN Transfer
..............................................418
CPU OUT Transfer
................................................372
Demand Transfer
Demand Transfer 2-Cycle Transfer
Demand Transfer Fly-by Transfer
................................................419
DMA IN Transfer
............................................420
DMA OUT Transfer
DMA Transfer and Interrupts
DMA Transfer during Sleep
DMA Transfer Request during External Hold
External Hold Request During DMA Transfer
Flow of Data During 2-Cycle Transfer
Flow of Data During Fly-By Transfer
If an External Pin Transfer Request is Reentered During
...............................................369
Transfer
If Another Transfer Request Occurs During Block Transfer
..........................................................369
Precautions for Control Transfer
Read and Write Timing Diagrams for DMA Block/
.........................................421
Step Transfer
Read and Write Timing Diagrams for DMA Demand
...............................................422
Transfer
Selection of the Transfer Sequence
Setting of Transfer Enable (BFOK) Bits during Control
...............................................448
Transfer
Setup Stage of Control Transfer
(Class and Vendor Commands and Some Standard
Commands[Get_Descriptor, Set_Descriptor, and
Synch_Frame])
Setup Stage of Control Transfer (Most Standard Commands)
..........................................................410
Simultaneous Occurrence of a DMA Transfer Request and
an External Hold Request
Status Stage of Control Transfer
(Class and Vendor Commands and Some Standard
Commands[Get_Descriptor, Set_Descriptor, and
Synch_Frame])
Status Stage of Control Transfer
(Most Standard Commands)
Step/Block Transfer 2-Cycle Transfer
Step/Block Transfer 2-Cycle Transfer Fly-by Transfer
..........................................................350
Timing Diagram for BULK IN Transfer
(Writing by CPU and Reading by USB)
Timing Diagram for BULK OUT Transfer
(Reading by CPU and Writing by USB)
Timing of the DREQ Pin Input for Continuing Transfer Over
the Same Channel
.................................................342
Transfer Address
Transfer Between External I/O and External Memory
..........................................................369
...................................62
........................414
..........................347
...........................348
.................................356
...................................362
............357
............357
.....................373
......................375
.............................449
..........................346
......................................411
.........................357
......................................412
......................412
......................349
.......436
.......438
...................................368
739
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