Appendix C Dot Clock Generation Pll - Fujitsu MB91319 Series Hardware Manual

APPENDIX C Dot Clock Generation PLL

APPENDIX C Dot Clock Generation PLL
The built-in dot clock generation PLL requires that the LPF be connected to the CP pin
as shown in Figure C-1.
■ Dot Clock Generation PLL
0.25 µm: EVA, FLASH
R
C1
The LPF constant depends on the oscillation frequency. Contact Fujitsu for the recommended
value of the LPF constant.
Table C-1 shows examples of recommended values.
Table C-1 Examples of Recommended Values of LPF Constant
Division ratio
HSYNC
(kHz)
n
15.75 1204
31.5 1304
33.75 1320
45 1404
48 1428
Even in the built-in PLL generating slicer clock, a CPO pin needs to be connected with the LPF
described below.
688
Figure C-1 CP0 Pin Connection
CP0
C2
Output
PLL
clock
(MHz)
m
(MHz)
2 37.93 18.96
1 41.08 41.08
1 44.55 44.55
1 63.18 63.18
1 68.54 68.54
0.18 µm: EVA, FLASH, MASK
R2
C1
CHG
VCO
[1:0]
VCO1 10
VCO2 10
VCO2 10
VCO3 10
VCO3 10
CP0
R1
VCI
C2
External LPF
R (Ω) C1 (µF) C2 (pF)
915 0.22 None
915 0.22 None
915 0.22 None
2k 0.068 2700
2k 0.068 2700