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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2.3
Transfer Source/Transfer Destination Address Setting
Registers (DMASA0 to 4/DMADA0 to 4)
The transfer source/transfer destination address setting registers (DMASA0 to 4/
DMADA0 to 4) control the operation of the DMAC channels. There is a separate register
for each channel.
■ Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/DMADA0 to 4)
Figure 16.2-4 shows the bit configuration of the transfer source/transfer destination address
setting registers (DMASA0 to 4/DMADA0 to 4).
Figure 16.2-4 Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers
bit
31
30
bit
15
14
bit
31
30
bit
15
14
The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4)
are a group of registers that store the transfer source/transfer destination addresses. Each
register is 32 bits.
[bit31 to bit0] DMASA (DMA Source Addr)*: Transfer source address setting
These bits set the transfer source address.
336
(DMASA0 to 4/DMADA0 to 4)
29
28
27
26
25
13
12
11
10
9
(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXXbit)
29
28
27
26
25
13
12
11
10
9
(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXXbit)
24
23
22
21
20
DMASA[31:16]
8
7
6
5
4
DMASA[15:0]
24
23
22
21
20
DMADA[31:16]
8
7
6
5
4
DMADA[15:0]
19
18
17
16
3
2
1
0
19
18
17
16
3
2
1
0
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