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CHAPTER 3 CPU AND CONTROL UNITS
[Clearing of the time base counter due to the device state]
All bits of the time base counter are cleared to 0 at the same time if the device enters one of
the following states:
•
Stop state
•
Settings initialization reset (INIT) state
Especially in the stop state, an interval interrupt of the time base timer may unintentionally be
generated because the time base counter is used to measure the oscillation stabilization wait
time. Before setting stop mode, therefore, disable time base timer interrupts to prevent the time
base timer from being used.
In any other state, time base timer interrupts are automatically disabled because an operation
initialization reset (RST) occurs.
■ Watch Timer
The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization
with the 32 kHz subclock. The operation of this timer is not affected by the clock source selection
or the clock divide-by rate.
The watch timer is used to measure the subclock stabilization wait time and perform processing
at fixed intervals using the subclock.
The watch timer performs incremental counting while the subclock is operating and is stopped
when bit1 (OSCD2 bit) of the standby control register (STCR) is set to1 so that the watch timer
enters stop mode. To prevent the watch timer from being stopped in stop mode, set the OSCD2
bit to 0 before the watch timer enters stop mode so that the subclock is not stopped.
Follow the procedure below for switching the clock source from the main clock to subclock using
the watch timer:
1. Set the watch timer for the oscillation stabilization wait time. If necessary, clear all bits of the
watch timer to 0.
2. Set bit11 (PLL2EN bit) of the clock source register (CLKR) to 1 to start subclock oscillation.
3. Use the watch timer to wait until the subclock is stabilized. At this time, use a watch interrupt
to secure the oscillation stabilization wait time.
4. After the subclock has been stabilized, use bit9 and bit8 (CLKS1 and CLKS0 bits) of the clock
source register (CLKR) to switch the clock source from the main clock to subclock. If the clock
source is switched to the subclock before the subclock is stabilized, an unstable clock is
supplied and subsequent operation is unpredictable. Be sure to switch to the subclock after
the subclock has been stabilized.
For more information on the watch timer, see "3.13 Watch Timer".
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