Table of Contents
Advertisement
14.2.1
Serial Mode Register (SMR)
The serial mode register (SMR) specifies the UART operating mode.
Set an operating mode while operation is stopped. Do not write to this register while
operation is in progress.
■ Serial Mode Register (SMR)
Figure 14.2-2 shows the bit configuration of the serial mode register (SMR).
Figure 14.2-2 Bit Configuration of the Serial Mode Register (SMR)
SMR
Address ch0 000063
ch1 00006B
ch2 000073
ch3 00007B
ch4 000083
The SMR specifies the UART operating mode. Set the operating mode while operation is
stopped. Do not write to this register during operation.
The following describes the functions of the serial mode register (SMR) bits.
[bit7, bit6] MD1, MD0 (MoDe select)
These bits select a UART operating mode.
Table 14.2-1 shows the settings for the UART operating modes.
Table 14.2-1 Settings for UART Operating Modes
Mode
0
1
2
−
Note:
In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave CPU can be
connected to one host CPU. Since this resource cannot identify the data format of received data,
however, only the master in multiprocessor mode is supported. Because the parity check function
cannot be used, set PEN of the SCR register to 0.
7
6
5
MD1
MD0
H
H
R/W R/W
H
H
H
MD1
MD0
0
0
0
1
1
0
1
1
4
3
2
CS0
W
Operating mode
Asynchronous (start-stop synchronization) normal mode
[initial value]
Asynchronous (start-stop synchronization)
multiprocessor mode
Clock synchronous mode
Setting disabled
CHAPTER 14 UART
1
0
Initial value
00--0---
B
259
Advertisement
Table of Contents
