Fujitsu MB91319 Series Hardware Manual page 168

CHAPTER 5 16-BIT RELOAD TIMER
■ Underflow Operation
An underflow is an event in which the counter value changes from 0000
underflow occurs at the count of [Reload register setting value + 1].
If the RELD bit of the control status register (TMCSR) is set to "1" when an underflow occurs, the
contents of the 16-bit reload register (TMRLR) are loaded and the count operation is continued. If
the RELD bit is set to "0", the counter stops at FFFF
An underflow sets the UF bit of the control status register (TMCSR) and, if the INTE bit is set to
"1", generates an interrupt request.
Figure 5.3-2 shows the timing chart of the underflow operation.
[RELD=1]
Count clock
Counter
Data load
Underflow set
[RELD=0]
Count clock
Counter
Underflow set
146
Figure 5.3-2 Timing Chart of the Underflow Operation
0000 Reload data
H
0000 FFFF
H
.
H
-1
H
to FFFF . Thus, an
H H
-1 -1