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■ Base Clock Division Setting Register 0 (DIVR0)
Figure 3.11-7 shows the configuration of the Base Clock Division Setting Register 0 (DIVR0) bits.
Figure 3.11-7 Configuration of Base Clock Division Setting Register 0 (DIVR0) Bits
Address: 00000486
Initial value (INIT)
Initial value (RST)
Base Clock Division Setting Register 0 (DIVR0) controls the divide-by rate of an internal clock in
relation to the base clock. This register sets the divide-by rates of the CPU clock, the clocks of an
internal bus (CLKB) and a peripheral circuit, and the peripheral bus clock (CLKP).
An upper-limit frequency for the operation is prescribed for each clock. If the combination of
source clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a
frequency exceeding this upper-limit frequency, operation is unpredictable. Be extremely careful
of the order in which you change the settings when selecting the source clock.
If the setting in this register is changed, the new frequency-divide-by rate takes effect for the clock
rate following the one during which the setting was made.
[bit15 to bit12] B3, B2, B1, B0 (clkB divide select 3-0)
These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clock
divide-by rate of the CPU, internal memory, and internal bus clock (CLKB). The values written
to these bits determine the divide-by rate (clock frequency) of the CPU and internal bus clock
in relation to the base clock, which can be selected from the 16 types shown in Table 3.11-5.
The upper-limit frequency for operation is 50 MHz. Do not set a divide-by rate that results in a
frequency exceeding this limit.
Table 3.11-5 Clock Divide-By Rate (CPU Clock ) Settings
B3
B2
B1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
...
...
...
1
1
1
φ: Frequency of the system base clock
•
These bits are initialized to 0000 by a reset (INIT).
•
These bits are readable and writable.
bit
15
14
B3
B2
H
R/W
R/W
0
0
x
x
B0
Clock divide-by rate
φ
0
φ × 2 (divided by 2)
1
φ × 3 (divided by 3)
0
φ × 4 (divided by 4)
1
φ × 5 (divided by 5)
0
φ × 6 (divided by 6)
1
φ × 7 (divided by 7)
0
φ × 8 (divided by 8)
1
...
...
φ × 16 (divided by 16)
1
CHAPTER 3 CPU AND CONTROL UNITS
13
12
11
10
B1
B0
P3
P2
R/W
R/W
R/W
R/W R/W
0
0
0
0
x
x
x
x
Clock frequency: if the source oscillation is
10 [MHz] and the PLL is multiplied by 4
40 [MHz] (initial value)
9
8
P1
P0
R/W
1
1
x
x
20 [MHz]
13.3 [MHz]
10 [MHz]
8 [MHz]
6.67 [MHz]
5.71 [MHz]
5 [MHz]
...
2.5 [MHz]
95
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