Table of Contents
Advertisement
CHAPTER 2 HANDLING THE DEVICE
Note:
Signal delay time between the X0 (X0A, X0B) and X1 (X1A, X1B) pins must be within
15 ns (operating at 10 MHz).
❍ Notes on using MS clock
For MSCLK, MS transfer clock signal is output externally from an internal I/O cell and then
reentered. Therefore, insert damping resistor exteriorly to reduce reflection noise that may affect
the internal circuit.
■ Limitations
❍ Common of MB91319 series
Clock controller
INIT must be kept at the L level until the oscillation stabilization wait time is reached.
Bit search module
Data register for detection 0 (BSD0), data register for detection 1 (BSD1), and data register for
change point detection BSDC are word access only.
I/O port
Only byte access is permitted for ports.
Low Power Consumption Mode
To switch to standby mode, use synchronous standby mode (set by the SYNCS bit, that is bit8
of the TBCR, time-base counter control register) and be sure to use the following sequence:
/* STCR write */
ldi
ldi
stb
/* CTBR write */
ldi
ldi
stb
ldi
stb
/* Time base counter is cleared here */
ldub
/* Synchronous standby transition start */
ldub
nop
nop
nop
nop
nop
When using the monitor debugger, do not:
•
Set a break point within the above sequence of instructions.
•
Step of the instructions within the above sequence of instructions.
26
#_STCR, r0
#val_of_Stby, rl
rl, @r0
#_CTBR, r2
#0xA5, rl
rl, @r2
#0x5A, rl
rl, @r2
@r0, rl
@r0, rl
; STCR register (0x0481)
; Val_of_Stby is write data to STCR
; Write to STCR
; CTBR register (0x0483)
; Clear command (1)
; Write A5 to CTBR
; Clear command (2)
; Write 5A to CTBR
; Read STCR
; Dummy read STCR
; nop ×5 for timing adjustment
Advertisement
Table of Contents
