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[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload
This bit controls reloading of the transfer source address register for the corresponding
channel.
If this bit enables reloading, the transfer source address register value is restored to its initial
value after the transfer is completed.
The details of other functions are the same as those described for bit22 (SADR).
Table 16.2-11 shows the specification of transfer destination address register reloading.
Table 16.2-12 Specification of Transfer Destination Address Register Reloading
DADR
0
Disables transfer destination address register reloading. (initial value)
1
Enables transfer destination address register reloading.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature
of the error that occurred is indicated by DSS2 to 0. Note that an interrupt occurs only for
specific termination causes and not for all termination causes. Refer to bits DSS2-0, which are
bit18 to bit16.
Table 16.2-13 shows the specification of the error interrupt request output permission.
Table 16.2-13 Specification of the Error Interrupt Request Output Permission
ERIE
0
Disables error interrupt request output. (initial value)
1
Enables error interrupt request output.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
[bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable
This bit controls the occurrence of an interrupt for normal termination.
Table 16.2-14 shows the specification of the end interrupt request output permission.
Table 16.2-14 Specification of the End Interrupt Request Output Permission
EDIE
0
Disables end interrupt request output. (initial value)
1
Enables end interrupt request output.
•
When reset: Initialized to 0.
•
This bit is readable and writable.
CHAPTER 16 DMA CONTROLLER (DMAC)
specification
Function
Function
Function
333
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