Data Register (Idar) - Fujitsu MB91319 Series Hardware Manual

15.2.8

Data Register (IDAR)

This section describes the configuration and functions of the data register (IDAR).
■ Data Register (IDAR)
Figure 15.2-12 shows the bit configuration of the data register (IDAR).
Address:
ch0 0000BD
ch1 0000CD
ch2 0000DD
ch3 0000ED
[bit7 to bit0] Data bits D7 to D0
Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB.
The writing side of this register has a double buffer. While the bus is busy (BB = 1), write data
is loaded into the register for serial transfer. When the INT bit (IBCR) is cleared or the bus is
idle (IBSR BB = 0), transfer data is loaded into the internal transfer register.
Since data is directly read from the register for serial transfer during reading, receive data in
this register is valid only while the INT bit (IBCR) is set.
Figure 15.2-12 Data Register (IDAR)
7
H
D7
H
H R/W
H Initial value 0
6 5 4 3
D6 D5 D4 D3
R/W R/W R/W R/W
0 0 0 0
2
CHAPTER 15 I C INTERFACE
2 1 0
D2 D1 D0
R/W R/W R/W
0 0 0
305