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CHAPTER 3 CPU AND CONTROL UNITS
Table 3.8-3 Vector Table (2 / 3)
Interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Time base timer overflow
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
Maskable interrupt source
56
Interrupt number
Decimal
*2
29
*2
30
*2
31
*2
32
*2
33
*2
34
*2
35
*2
36
*2
37
*2
38
*2
39
*2
40
*2
41
*2
42
*2
43
*2
44
*2
45
*2
46
47
*2
48
*2
49
*2
50
*2
51
*2
52
*2
53
*2
54
*2
55
*2
56
*2
57
*2
58
Interrupt level
Hexadecimal
1D
ICR13
1E
ICR14
1F
ICR15
20
ICR16
21
ICR17
22
ICR18
23
ICR19
24
ICR20
25
ICR21
26
ICR22
27
ICR23
28
ICR24
29
ICR25
2A
ICR26
2B
ICR27
2C
ICR28
2D
ICR29
2E
ICR30
2F
ICR31
30
ICR32
31
ICR33
32
ICR34
33
ICR35
34
ICR36
35
ICR37
36
ICR38
37
ICR39
38
ICR40
39
ICR41
3A
ICR42
Default
Offset
address of
TBR
388
000FFF88
H
H
384
000FFF84
H
H
380
000FFF80
H
H
37C
000FFF7C
H
H
378
000FFF78
H
H
374
000FFF74
H
H
370
000FFF70
H
H
36C
000FFF6C
H
H
368
000FFF68
H
H
364
000FFF64
H
H
360
000FFF60
H
H
35C
000FFF5C
H
H
358
000FFF58
H
H
354
000FFF54
H
H
350
000FFF50
H
H
34C
000FFF4C
H
H
348
000FFF48
H
H
344
000FFF44
H
H
340
000FFF40
H
H
33C
000FFF3C
H
H
338
000FFF38
H
H
334
000FFF34
H
H
330
000FFF30
H
H
32C
000FFF2C
H
H
328
000FFF28
H
H
324
000FFF24
H
H
320
000FFF20
H
H
31C
000FFF1C
H
H
318
000FFF18
H
H
314
000FFF14
H
H
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