Table of Contents
Advertisement
CHAPTER 3 CPU AND CONTROL UNITS
3.10.5
Reset Operation Modes
Two modes for an operation initialization reset (RST) are provided: normal
(asynchronous) reset mode and synchronous reset mode. The operation initialization
reset mode is selected with bit7 (SYNCR bit) of the time base counter control register
(TBCR). This mode setting is initialized only by a settings initialization reset (INIT). A
settings initialization reset always results in an asynchronous reset.
This section describes the operation of these modes.
■ Normal Reset Operation
Normal reset operation refers to a transition to the operation initialization rest (RST) state
immediately after an operation initialization reset (RST) request.
If a rest (RST) request is accepted in this mode, the device immediately enters the reset (RST)
state regardless of the status of internal bus access.
In this mode, the result of a bus access being performed prior to each state transition is
unpredictable. However, these requests can certainly be accepted.
If bit7 (SYNCR bit) of the time base counter control register (TBCR) is set to 0, normal reset
mode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode.
■ Synchronous Reset Operation
Synchronous reset operation refers to a transition to the operation initialization reset (RST) state
after all bus access has stopped when an operation initialization reset (RST) request occurs.
Even if a reset (RST) request is accepted in this mode, the device does not enter the reset (RST)
state while internal bus access is in progress.
If the above request is accepted, a sleep request is issued to the internal buses. If all the buses
stop and enter the sleep state, the device enters the operation initialization reset (RST) state.
In this mode, the result of all bus accesses is guaranteed because all bus access is stopped prior
to each status transition.
If bus access does not stop for some reason, no requests can be accepted while the bus access
is in progress. Even in this case, the settings initialization reset (INIT) is immediately valid.
Bus access may not stop in the following cases:
•
A bus release request (BRQ) continues to be input to the external extended bus interface, bus
release acknowledge (BGRNT) is valid, and a new bus access request arrives from an internal
bus.
•
A ready request (RDY) continues to be input to the external extended bus interface and bus
wait is valid. In the following cases, the device eventually enters another state but only after a
long time:
Reference:
For details on using software reset of synchronous mode, see restrictions of bit7: SYNCR bit of TBCR (time
base counter control register).
The DMA controller, which stops transfer when a request is accepted, does not delay transition to another
state. If bit7 (SYNCR bit) of the time base counter control register (TBCR) is set to 1, synchronous reset mode
is selected. The initial value after a settings initialization reset (INIT) is normal reset mode.
74
Advertisement
Table of Contents
