Table of Contents
Advertisement
CHAPTER 16 DMA CONTROLLER (DMAC)
[bit18 to bit16] DSS2 to DSS0 (DMA Stop Status)*: Transfer stop source indication
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or
termination of DMA transfer on the corresponding channel. For a list of end codes, see Table
16.2-15.
Table 16.2-15 End Codes
DSS
000
x01
x10
x11
1xx
The code indicating a transfer stop request is set only if the request is received from a peripheral
circuit and the external pin DSTP function is used.
The Interrupt column indicates the type of interrupts that can occur.
•
When reset: Initialized to 000.
•
These bits can be cleared by writing 000 to them.
•
These bits are readable and writable. Note, however, that the only valid written value is 000.
[bit15 to bit8] SASZ (Source Addr count SiZe)*: Transfer source address count size
These bits specify the increment or decrement width for the transfer source address (DMASA)
of the corresponding channel for each transfer operation. The value set by these bits becomes
the address increment/decrement width for each transfer unit. The address increment/
decrement width conforms to the instruction in the transfer source address count mode
(SADM).
Table 16.2-16 shows the specification of the transfer source address count size.
Table 16.2-16 Specification of the Transfer Source Address Count Size
SASZ
XXXX
•
When reset: Not initialized
•
These bits are readable and writable.
334
Function
Initial value
Address error (underflow/overflow)
Transfer stop request
Normal end
DMA stopped temporarily (due, for example, to
DMAH, PAUS bit, and an interrupt)
Specify the increment/decrement width of the transfer source address. 0 to 255
None
Error
Error
End
None
specification
Function
Interrupt
Advertisement
Table of Contents
