Bus Control Register (Ibcr) - Fujitsu MB91319 Series Hardware Manual

2
CHAPTER 15 I C INTERFACE
15.2.2

Bus Control Register (IBCR)

This section describes the configuration and functions of the bus control register
(IBCR).
■ Bus Control Register (IBCR)
Figure 15.2-3 shows the bit configuration of the bus control register (IBCR).
Figure 15.2-3 Bit Configuration of the Bus Control Register (IBCR)
Address:
ch0 0000B4
ch1 0000C4
ch2 0000D4
ch3 0000E4
Bits other than BER and BEIE are cleared if the I
[bit15] BER (Bus ERror)
This bit is the bus error interrupt request flag bit.
For a read by a read modify instruction, 1 is always read.
During writing
0
1
During reading
0
1
If this bit is set, the EN bit of the CCR register is cleared, the I
transfer is halted. All bits of the IBSR and IBCR registers except BER and BEIE are cleared.
Clear this bit before the I
This bit is set to 1 if:
• An illegal START or STOP condition at a specific location is detected (while an slave address
or data is being transferred).
• The header section of a slave address is received during a 10-bit read access before 10-bit
write access with the first byte is performed.
• A STOP condition is detected during transfer in master mode.
*: When the I
condition is received to prevent an incorrect bus error report from being issued.
292
15
H
BER BEIE
H
R/W
H
0
H Initial value
Clears the bus error interrupt request flag.
Has no meaning.
Bus error not detected
Error condition detected
2
C interface is enabled (EN = 1) again.
*
2
C interface is enabled during transfer, this detection flag is set after the first STOP
14 13 12 11
SCC MSS ACK GCAA INTE
R/W W R/W R/W
0 0 0 0
2
C interface is stopped (ICCR EN=0).
*
10 9 8
INT
R/W R/W R/W
0 0 0
2
C interface is stopped, and data