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CHAPTER 17 USB FUNCTION
■ Read and Write Timing Diagrams for DMA Demand Transfer
FR corresponds to that of demand transfer.
Figure 17.3-6 shows the read and write timing diagrams for DMA block transfer.
Figure 17.3-6 Read and Write Timing Diagrams for DMA Block Transfer
(Writing)
FMCLK0
DREQ2
DACK2
WR
DATAI[15:0]
Note 2:
Data is written to the FIFO buffer at the
last rising edge of FMCLK0 while WR is
at the low level.
(Reading)
FMCLK
DREQ
DACK
RD
[DATA[15:0]
DATAOE
422
Valid data
DATAI must not be changed
while WR is at the low level.
Output of valid data
DREQ is negated at the first rising
edge of FMCLK0 after the last
RD for reading of one packet is asserted.
Note 1: Frequency of FMCLK0 is 13 MHz or more.
Last data
Valid data
DREQ is negated at the first rising edge of
FMCLK0 after the last WR for writing of
one packet is asserted.
WR requires a deassertion period of two or more
FMCLK0 cycles.
Note 1: Frequency of FMCLK0 is 13 MHz or more.
RD requires a deassertion
period of one or more
FMCLK0 cycles.
Note 2:
The same signal input
timing is applicable to the
DACKn signal and RD or
WR signal.
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