Table of Contents
Advertisement
CHAPTER 16 DMA CONTROLLER (DMAC)
16.2.4
All-Channel Control Register (DMACR)
The all-channel control register (DMACR) controls the operation of the all five DMAC
channels. Be sure to access this register using byte length.
■ All-Channel Control Register (DMACR)
Figure 16.2-5 shows the bit configuration of the DMAC all-channel control register (DMACR).
Figure 16.2-5 Bit Configuration of the All-Channel Control Register (DMACR)
bit
31
30
-
DMAE
bit
15
14
-
-
[bit31] DMAE (DMA Enable): DMA operation enable
This bit controls the operation of all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled
regardless of the start/stop settings for each channel and the operating status. Any channel
carrying out transfer cancels the requests and stops transfer at a block boundary. All start
operations on each channel in a disabled state are disabled.
If this bit enables DMA operation, start/stop operations are enabled for all channels. Simply
enabling DMA operation with this bit does not activate each channel.
DMA operation can be forced to stop by writing 0 to this bit. However, be sure to force
stopping (0 write) only after temporarily stopping DMA using the DMAH[3:0] bits [bit27 to bit24
of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMA
stops, but the transfer data cannot be guaranteed. Check whether DMA is stopped using the
DSS[2:0] bits [bit18 to bit16 of DMACB].
Table 16.2-18 shows the specification of the DMA operation permission.
Table 16.2-18 Specification of the DMA Operation Permission
DMAE
0
1
•
When reset: Initialized to 0.
•
This bit is readable and writable.
338
29
28
27
26
25
-
PM01
DMAH[3:0]
13
12
11
10
9
-
-
-
-
-
(Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX_bit)
Disables DMA transfer on all channels. (initial value)
Enables DMA transfer on all channels.
24
23
22
21
20
-
-
-
-
8
7
6
5
4
-
-
-
-
-
Function
19
18
17
16
-
-
-
-
3
2
1
0
-
-
-
-
Advertisement
Table of Contents
