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CHAPTER 16 DMA CONTROLLER (DMAC)
16.2.1
Control/Status Registers A (DMACA0 to DMACA4)
Control/status registers A (DMACA0 to DMACA4) control the operation of the DMACA
channels. There is a separate register for each channel.
■ Control/Status Registers A (DMACA0 to DMACA4)
Figure 16.2-2 shows the bit configuration of control/status registers A (DMACA0 to DMACA4).
Figure 16.2-2 Bit Configuration of Control/Status Registers A (DMACA0 to DMACA4)
bit
31
30
DENB
PAUS
bit
15
14
[bit31] DENB (Dma ENaBle): DMA operation enable bit
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.
The activated channel starts DMA transfer when a transfer request is generated and
accepted.
All transfer requests that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to 0 and
transfer stops.
The transfer can be forced to stop by writing 0 to this bit. Be sure to stop a transfer forcibly (0
write) only after temporarily stopping DMA using the PUAS bit [bit30 of DMACA]. If the transfer
is forced to stop without first temporarily stopping DMA, DMA stops but the transferred data
cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [bit18 to bit16
of DMACB].
DENB
0
1
•
If a stop request is accepted during reset: Initialized to 0.
•
This bit is readable and writable.
If the operation of all channels is disabled by bit15 (DMAE bit) of the DMAC all-channel control
register (DMACR), writing 1 to this bit is disabled and the stopped state is maintained. If the
operation is disabled by the above bit while it is enabled by this bit, 0 is written to this bit and the
transfer is stopped (forced stop).
324
29
28
27
26
25
IS[4:0]
STRG
13
12
11
10
(Initial value: 00000000_0000XXXX_XXXXXXXX_XXXXXXXX bit)
Disables operation of DMA on the corresponding channel (initial value).
Enables operation of DMA on the corresponding channel.
24
23
22
21
DDNO[3:0]
9
8
7
6
5
DTC[15:0]
Function
20
19
18
17
16
BLK[3:0]
4
3
2
1
0
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