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CHAPTER 3 CPU AND CONTROL UNITS
3.8.1
EIT Interrupt Levels
The interrupt levels are 0 to 31 and are managed with five bits.
■ Interrupt Levels
Table 3.8-1 shows the allocation of the levels.
Table 3.8-1 EIT Interrupt Levels
Binary
00000
...
...
00011
00100
00101
...
...
01110
01111
10000
10001
...
...
11110
11111
Operation is possible for levels 16 to 31.
The interrupt level does not affect an undefined instruction exception, no-coprocessor trap,
coprocessor error trap, or an INT instruction. It does not change the ILM, either.
■ I Flag
A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as bit4 of
the PS register.
Value
Interrupts prohibited
0
Cleared to 0 if the INT instruction is executed.
(Note that a value saved on the stack is the value before it is cleared.)
Interrupts permitted
1
The mask processing of an interrupt request is controlled by the value in the ILM register.
50
Level
Decimal
0
(Reserved for system)
...
...
...
...
3
(Reserved for system)
4
INTE instruction
Step trace trap
(Reserved for system)
5
...
...
...
...
(Reserved for system)
14
15
NMI (for user)
16
Interrupt
17
Interrupt
...
...
...
...
30
Interrupt
31
-
If the original ILM value is between
16 and 31, a program cannot set a
value in this ILM range.
User interrupts prohibited if ILM is set
Interrupts prohibited if ICR is set
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