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[bit14] BEIE (Bus Error Interrupt Enable)
This bit is the bus error interrupt enable bit.
0
1
An interrupt occurs if this bit is set to 1 and the BER bit is set to 1.
[bit13] SCC (Start Condition Continue)
This bit is the repeated [START] condition generation bit.
During writing
0
1
The read value of this bit is always 0.
If 1 is written to this bit in master mode (MSS = 1, INT = 1), a repeated START condition is
generated and the INT bit is automatically cleared.
[bit12] MSS (Master Slave Select)
This bit is the master or slave selection bit.
0
1
This bit is cleared when arbitration lost occurs during master transmission, causing slave mode to
start.
Write 0 to this bit during a master interrupt (MSS=1, INT=1) to automatically clear the INT bit.
Then, generate a [STOP] condition to end the transfer.
Note:
The MSS bit functions as a direct reset. To detect a STOP condition, check the BB bit of the IBSR
register.
If 1 is written to this bit while the bus is idle (MSS = 0, BB = 0), a START condition is generated and
the value of IDAR is sent.
If 1 is written to this bit while the bus is busy (BB = 1, TRX = 0, MSS = 0), the I
transmission when the bus becomes idle. If the I
that is accompanied by a write access during this time, the bus becomes idle after the transfer ends.
If the interface is transmitting as a slave (IBCR AAS = 1, TRX = 1) during this time, no data is sent
even if the bus has become idle. It is important to check whether the I
slave (IBSR AAS = 1), and whether data transmission has ended normally (IBCR MSS = 1) at the
next interrupt or otherwise data transmission has failed with an error (IBSR AL = 1).
When using in the following condition, transmission of general call address is prohibited since
reception as a slave cannot be performed.
ln addition to this LSl, if another LSI that becomes master mode exists on the bus, this LSI sends
general call address as a master, and arbitration lost occurs at the second byte or later.
Bus error interrupt disabled
Bus error interrupt enabled
Has no meaning.
Generates a repeated START condition in master transfer.
Selects slave mode.
Selects master mode. Generates a START condition to enable the
value of the IDAR register to be sent as a slave address.
CHAPTER 15 I
2
C interface is specified as the address for a slave
2
C interface is specified as a
2
C INTERFACE
2
C interface starts
293
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