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■ Main Clock Oscillation Stabilization Wait Timer (for the Subclock Select)
The main clock oscillation stabilization wait timer is a 26-bit free-run timer that performs
incremental counting in synchronization with the main clock. The operation of this timer is not
affected by the clock source selection or the clock divide-by rate.
The main clock oscillation stabilization wait timer is used to measure the main clock oscillation
stabilization wait time.
Main clock oscillation can be controlled by bit0 (OSCDS1 bit) of the oscillation control register
(OSCCR) while the device is operating on the subclock. This timer is used to measure the
oscillation stabilization wait time when main clock oscillation is restarted after it has been
stopped.
Follow the procedure below for switching the clock source to the main clock when the device is
operating on the subclock with the main clock stopped.
1. Clear the main clock oscillation stabilization wait timer.
2. Set bit0 (OSCDS1 bit) of the oscillation control register (OSCCR) to 0 to start main clock
oscillation.
3. Use the main clock oscillation stabilization wait timer to wait until the main clock oscillation is
stabilized.
4. After the main clock has been stabilized, use bit9 and bit8 (CLKS1 and CLKS0 bits) of the
clock source register (CLKR) to switch the clock source from the main clock to subclock. If the
clock source is switched to the main clock before the main clock is stabilized, an unstable
clock is supplied and subsequent operation is unpredictable. Be sure to switch to the main
clock after the main clock has been stabilized.
For more information on the main clock oscillation stabilization wait timer, see "3.14 Main Clock
Oscillation Stabilization Wait Timer".
■ Peripheral Stop Control
Peripheral stop control is used to control the clock supply to peripheral resources.
Power saving can be implemented by stopping the clock supply to peripheral resources not being
used.
For details, refer to Peripheral stop control.
CHAPTER 3 CPU AND CONTROL UNITS
103
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